GNU nano - Patches: patch #9356, syntax highlighting for Verilog
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patch #9356: syntax highlighting for Verilog
Submitter: | Ben Rosser <tc01> | ||
Submitted: | Wed 24 May 2017 02:56:54 PM UTC | ||
Priority: | 3 - Low | Status: | Wont Do |
Privacy: | Public | Assigned to: | None |
Open/Closed: | Closed | Release: | None |
Sun 26 Sep 2021 03:02:23 PM UTC, comment #1: |
Benno Schulenberg <bens> |
Wed 24 May 2017 02:56:54 PM UTC, original submission:
I recently found myself working with the Verilog hardware description language and was disappointed to find no syntax highlighting for it in nano. So I decided to do something about this.
|
Ben Rosser <tc01> |
Depends on the following items: None found
Items that depend on this one: None found
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Follow 5 latest changes.
Date | Changed by | Updated Field | Previous Value | => | Replaced by |
---|---|---|---|---|---|
2021-09-26 | bens | Status | None | Wont Do | |
Open/Closed | Open | Closed | |||
2018-04-25 | bens | Priority | 5 - Normal | 3 - Low | |
Summary | Add Verilog nanorc file for syntax highlighting | syntax highlighting for Verilog | |||
2017-05-24 | tc01 | Attached File | - | Added 0001-Add-Verilog-nanorc-file-for-syntax-highlighting.patch, #40781 |
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Corresponding source code
The author of another Verilog syntax (see patch #10015) claims that his syntax is cleaner and more complete [1]. Whether or not you disagree with him, comments are welcome (on that patch or on the mailing list).
[1] https://lists.gnu.org/archive/html/nano-devel/2021-01/msg00023.html