Gnu Circuit Analysis Package - Support: sr #111143, Capabilities of Verilog AMS...

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sr #111143: Capabilities of Verilog AMS translator

Submitter:	None
Submitted:	Thu 31 Oct 2024 12:25:48 AM UTC


Category:	None	Priority:	5 - Normal
Severity:	1 - Wish	Status:	None
Privacy:	Public	Assigned to:	None
Originator Email:	-email is unavailable-	Open/Closed:	Open
Operating System:	GNU/Linux

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Mon 25 Nov 2024 01:54:01 PM UTC, comment #1:

> which parts of standard were implemented? I am interested in generative abilities of verilog a - generating internal nodes on the fly in for loop for example. What about digital part and multidisciplinary support?

Hi George. Sorry I have not seen your enquiry earlier.

Hierarchy is fully supported and "generate" is definitely intended. There are various README files in the modelgen-verilog repo that also cover status. Generally, we are able to prioritise features upon user request.

On the multidisciplinary end, Gnucap has the infrastructure and devices for mixed mode simulation. This will be exposed by means of disciplines and connect modules, see e.g. LRM 9.23.

Performance will improve as we proceed. Correctness and scalability are a priority right now. Feel free to share example inputs that you think should run faster.

Thanks
felix

felix salfelder <felixs>

Thu 31 Oct 2024 12:25:48 AM UTC, original submission:

Hello!
It seems that development of open-vaf was suspended, and the implementation of many important parts of standard won't be added in foreseeable future. And I encountered this project, looks awesome 👍
So I have a few questions if possible:
1) which parts of standard were implemented? I am interested in generative abilities of verilog a - generating internal nodes on the fly in for loop for example. What about digital part and multidisciplinary support?
2) is there any performance comparisons with open-vaf or adms?
3) how good is convergence of complex models?

Thank you in advance, George.

Anonymous

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Gnu Circuit Analysis Package - Support: sr #111143, Capabilities of Verilog AMS...

sr #111143: Capabilities of Verilog AMS translator

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