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Architecture

  1. The IISC architecture consists of an unlimited number of 128 bit temporary registers, four 64 bit special purpose registers, and a linear address space consisting of 264 (or 1.84467440737e+19) individually addressable bytes.

  2. The IISC architecture is intended to be translated to instructions for an existing hardware instruction set before execution.

Registers

  1. The special purpose registers are...

  2. All temporary registers are capable of holding all single-register data types available in the IISC instruction set.

  3. All special purpose registers are capable of holding all data types that are 64 bits or less in size.

  4. Data written directly to a special purpose register is not guaranteed to be preserved for future reading after it has been written as further instruction execution may automatically change the value in some registers.

Register Data Types

  1. IISC has a number of single-register data types called word data types. Each of these data types is represented by 64 bits or less of precision.

  2. The IISC word-oriented data types are...

    TypeSizePrecision
    Signed Double Word128b-2127 ... 2127
    Unsigned Double Word0 ... 2128
    Signed Word64b-263 ... 263
    Unsigned Word0 ... 264
    Large Floating Point-
    Memory Address0 ... 264
    Signed Half-word32b-2147483648 ... 2147483647
    Unsigned Half-word0 ... 4294967295
    Small Floating Point
    Signed Quarter-word16b-32768 ... 32767
    Unsigned Quarter-word0 ... 65535
    Signed Byte8b-128 ... 127
    Unsigned Byte0 ... 255
  3. The binary format of word-oriented data types is implementation dependent.

  4. Unsigned word data types (Unsigned Word, Unsigned Half-word, Unsigned Quarter-word, Unsigned Byte) represent whole positive numbers starting with zero and continuing until a certain precision of maximum value.

  5. Signed word data types (Signed Word, Signed Half-word, Signed Quarter-word, Signed Byte) represent whole positive or negative numbers with the range of values being determined by the precision of the type.

  6. The Large and Small Floating Point data types correspond to the Single (32b) and Double (64b) precision binary floating point representations specified in the IEEE 754 standard for floating point representations.

  7. As all data types are binary, the contents of registers may be treated as any type. It is not recommended to ignore binary representation formats as this will have negative effects on the reliability of a program.

Memory Model

  1. IISC does not enforce a specific memory model. Various memory addressing modes may be used by the underlying hardware.

  2. An implementation may support a smaller address space than 2^64 addresses.

  3. IISC explicitly has no endianness. Endianness is only introduced when IISC is translated to a hardware architecture that requires endianness. Individual bytes of a single-register value stored in memory may still be read and oriented into a register according to a certain endianness pattern, but the resulting value held in the register is not guaranteed to be the same as the value stored in memory.