The IISC architecture consists of an unlimited number of 128 bit temporary registers, four 64 bit special purpose registers, and a linear address space consisting of 264 (or 1.84467440737e+19) individually addressable bytes.
The IISC architecture is intended to be translated to instructions for an existing hardware instruction set before execution.
The special purpose registers are...
The stack register can be used to hold the top of a program stack structure.
The base register can be used to hold the base of the program stack segment or the base address of the writeable section of memory provided to the program.
The zero register holds a static value of zero at all times. It cannot be written to.
The instruction register holds the address of the current instruction.
All temporary registers are capable of holding all single-register data types available in the IISC instruction set.
All special purpose registers are capable of holding all data types that are 64 bits or less in size.
Data written directly to a special purpose register is not guaranteed to be preserved for future reading after it has been written as further instruction execution may automatically change the value in some registers.
IISC has a number of single-register data types called word data types. Each of these data types is represented by 64 bits or less of precision.
The IISC word-oriented data types are...
Type | Size | Precision |
---|---|---|
Signed Double Word | 128b | -2127 ... 2127 |
Unsigned Double Word | ⋮ | 0 ... 2128 |
Signed Word | 64b | -263 ... 263 |
Unsigned Word | ⋮ | 0 ... 264 |
Large Floating Point | ⋮ | - |
Memory Address | ⋮ | 0 ... 264 |
Signed Half-word | 32b | -2147483648 ... 2147483647 |
Unsigned Half-word | ⋮ | 0 ... 4294967295 |
Small Floating Point | ⋮ | |
Signed Quarter-word | 16b | -32768 ... 32767 |
Unsigned Quarter-word | ⋮ | 0 ... 65535 |
Signed Byte | 8b | -128 ... 127 |
Unsigned Byte | ⋮ | 0 ... 255 |
The binary format of word-oriented data types is implementation dependent.
Unsigned word data types (Unsigned Word, Unsigned Half-word, Unsigned Quarter-word, Unsigned Byte) represent whole positive numbers starting with zero and continuing until a certain precision of maximum value.
Signed word data types (Signed Word, Signed Half-word, Signed Quarter-word, Signed Byte) represent whole positive or negative numbers with the range of values being determined by the precision of the type.
The Large and Small Floating Point data types correspond to the Single (32b) and Double (64b) precision binary floating point representations specified in the IEEE 754 standard for floating point representations.
As all data types are binary, the contents of registers may be treated as any type.
IISC does not enforce a specific memory model. Various memory addressing modes may be used by the underlying hardware.
An implementation may support a smaller address space than 2^64 addresses.
IISC explicitly has no endianness.
Endianness is only introduced when IISC is translated to a hardware architecture that requires endianness.