JIT_OP_LSHL: [=lreg, lreg, reg("ecx")] -> { unsigned char *patch; if($1 != $2) x86_mov_reg_reg(inst, $1, $2, 4); if(%1 != %2) x86_mov_reg_reg(inst, %1, %2, 4); x86_alu_reg_imm(inst, X86_AND, X86_ECX, 0x3f); x86_alu_reg_imm(inst, X86_CMP, X86_ECX, 32); patch = inst; x86_branch8(inst, X86_CC_C, 0, 0); x86_mov_reg_reg(inst, %1, $1, 4); x86_alu_reg_reg(inst, X86_XOR, $1, $1); x86_patch(patch, inst); x86_shld_reg(inst, %1, $1); x86_shift_reg(inst, X86_SHL, $1); } JIT_OP_LSHR: [=lreg, lreg, reg("ecx")] -> { unsigned char *patch; if($1 != $2) x86_mov_reg_reg(inst, $1, $2, 4); if(%1 != %2) x86_mov_reg_reg(inst, %1, %2, 4); x86_alu_reg_imm(inst, X86_AND, X86_ECX, 0x3f); x86_alu_reg_imm(inst, X86_CMP, X86_ECX, 32); patch = inst; x86_branch8(inst, X86_CC_LT, 0, 0); x86_mov_reg_reg(inst, $1, %1, 4); x86_shift_reg_imm(inst, X86_SAR, %1, 31); x86_patch(patch, inst); x86_shrd_reg(inst, $1, %1); x86_shift_reg(inst, X86_SAR, %1); } JIT_OP_LSHR_UN: [=lreg, lreg, reg("ecx")] -> { unsigned char *patch; if($1 != $2) x86_mov_reg_reg(inst, $1, $2, 4); if(%1 != %2) x86_mov_reg_reg(inst, %1, %2, 4); x86_alu_reg_imm(inst, X86_AND, X86_ECX, 0x3f); x86_alu_reg_imm(inst, X86_CMP, X86_ECX, 32); patch = inst; x86_branch8(inst, X86_CC_LT, 0, 0); x86_mov_reg_reg(inst, $1, %1, 4); x86_alu_reg_reg(inst, X86_XOR, %1, %1); x86_patch(patch, inst); x86_shrd_reg(inst, $1, %1); x86_shift_reg(inst, X86_SHR, %1); }