diff --git a/linux-2.6.32.60-mach-moxart/.project b/linux-2.6.32.60-mach-moxart/.project
new file mode 100644
index 0000000..ad1b755
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/.project
@@ -0,0 +1,78 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>linux-2.6.32.60</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
+					<value>clean</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/tmp/linux-2.6.32.60/arch/arm/Kconfig b/linux-2.6.32.60-mach-moxart/arch/arm/Kconfig
index b68faef..4e74f05 100644
--- a/tmp/linux-2.6.32.60/arch/arm/Kconfig
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/Kconfig
@@ -272,6 +272,15 @@ config ARCH_GEMINI
 	help
 	  Support for the Cortina Systems Gemini family SoCs
 
+config ARCH_MOXART
+    bool "MOXA ART SoC"
+    select CPU_FA526
+    help
+      Support for the MOXA ART SoC. This is a Faraday FA526 ARMv4 32-bit 192 MHz processor with MMU and 16KB/8KB D/I-cache (UC-7112-LX)
+      This perticular processor is used on models UC-7101, UC-7112/UC-7110, IA240/IA241, IA3341.
+      
+	  These are DIN-rail / wall-mountable embedded PCs sold by MOXA ( http://www.moxa.com/product/Embedded_Computers.htm ).
+
 config ARCH_EBSA110
 	bool "EBSA-110"
 	select CPU_SA110
@@ -712,6 +721,8 @@ source "arch/arm/mach-footbridge/Kconfig"
 
 source "arch/arm/mach-gemini/Kconfig"
 
+source "arch/arm/mach-moxart/Kconfig"
+
 source "arch/arm/mach-integrator/Kconfig"
 
 source "arch/arm/mach-iop32x/Kconfig"
diff --git a/tmp/linux-2.6.32.60/arch/arm/Makefile b/linux-2.6.32.60-mach-moxart/arch/arm/Makefile
index a73caaf..49977fc 100644
--- a/tmp/linux-2.6.32.60/arch/arm/Makefile
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/Makefile
@@ -125,6 +125,7 @@ machine-$(CONFIG_ARCH_DAVINCI)		:= davinci
 machine-$(CONFIG_ARCH_EBSA110)		:= ebsa110
 machine-$(CONFIG_ARCH_EP93XX)		:= ep93xx
 machine-$(CONFIG_ARCH_GEMINI)		:= gemini
+machine-$(CONFIG_ARCH_MOXART)       := moxart
 machine-$(CONFIG_ARCH_H720X)		:= h720x
 machine-$(CONFIG_ARCH_INTEGRATOR)	:= integrator
 machine-$(CONFIG_ARCH_IOP13XX)		:= iop13xx
diff --git a/tmp/linux-2.6.32.60/arch/arm/boot/compressed/head.S b/linux-2.6.32.60-mach-moxart/arch/arm/boot/compressed/head.S
index 61b3a33..5588c87 100644
--- a/tmp/linux-2.6.32.60/arch/arm/boot/compressed/head.S
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/boot/compressed/head.S
@@ -9,6 +9,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/linkage.h>
+#include <asm/mach-types.h>
 
 /*
  * Debugging stuff
@@ -127,7 +128,8 @@ start:
 		.word	0x016f2818		@ Magic numbers to help the loader
 		.word	start			@ absolute load/run zImage address
 		.word	_edata			@ zImage end address
-1:		mov	r7, r1			@ save architecture ID
+1:		ldr r1, =MACH_TYPE_MOXART
+		mov	r7, r1			@ save architecture ID
 		mov	r8, r2			@ save atags pointer
 
 #ifndef __ARM_ARCH_2__
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/configs/moxart_uc7112lx_defconfig b/linux-2.6.32.60-mach-moxart/arch/arm/configs/moxart_uc7112lx_defconfig
new file mode 100644
index 0000000..8d99dd1
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/configs/moxart_uc7112lx_defconfig
@@ -0,0 +1,1043 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.60
+# Fri Nov 30 13:53:12 2012
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_BASE_FULL is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+# CONFIG_SIGNALFD is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+CONFIG_SHMEM=y
+# CONFIG_AIO is not set
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=1
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+CONFIG_ARCH_MOXART=y
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+
+#
+# MOXA ART SoC Implementation
+#
+CONFIG_MACH_UC7112LX=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_FA526=y
+CONFIG_CPU_32v4=y
+CONFIG_CPU_ABRT_EV4=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_CACHE_FA=y
+CONFIG_CPU_COPY_FA=y
+CONFIG_CPU_TLB_FA=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="console=ttyS0,115200n8 root=/dev/mtdblock2 rootfstype=jffs2 rw"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+CONFIG_NF_CONNTRACK=y
+# CONFIG_NF_CT_ACCT is not set
+# CONFIG_NF_CONNTRACK_MARK is not set
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+# CONFIG_NF_CT_PROTO_DCCP is not set
+# CONFIG_NF_CT_PROTO_SCTP is not set
+# CONFIG_NF_CT_PROTO_UDPLITE is not set
+# CONFIG_NF_CONNTRACK_AMANDA is not set
+# CONFIG_NF_CONNTRACK_FTP is not set
+# CONFIG_NF_CONNTRACK_H323 is not set
+# CONFIG_NF_CONNTRACK_IRC is not set
+# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
+# CONFIG_NF_CONNTRACK_PPTP is not set
+# CONFIG_NF_CONNTRACK_SANE is not set
+# CONFIG_NF_CONNTRACK_SIP is not set
+# CONFIG_NF_CONNTRACK_TFTP is not set
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NETFILTER_XTABLES=y
+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
+# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
+# CONFIG_NETFILTER_XT_MATCH_HL is not set
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+# CONFIG_NETFILTER_XT_MATCH_STATE is not set
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_NF_CONNTRACK_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=y
+# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
+# CONFIG_IP_NF_MATCH_AH is not set
+# CONFIG_IP_NF_MATCH_ECN is not set
+# CONFIG_IP_NF_MATCH_TTL is not set
+# CONFIG_IP_NF_FILTER is not set
+# CONFIG_IP_NF_TARGET_LOG is not set
+# CONFIG_IP_NF_TARGET_ULOG is not set
+# CONFIG_IP_NF_MANGLE is not set
+# CONFIG_IP_NF_TARGET_TTL is not set
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_UC7112LX=y
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_ARM_AT91_ETHER is not set
+CONFIG_MOXART_ETHER=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/Kconfig b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/Kconfig
new file mode 100644
index 0000000..3c5f2ce
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/Kconfig
@@ -0,0 +1,12 @@
+if ARCH_MOXART
+
+menu "MOXA ART SoC Implementation"
+
+config MACH_UC7112LX
+	bool "MOXA UC-7112-LX"
+	help
+	  Say Y here if you intend to run this kernel on a MOXA UC-7112-LX embedded computer.
+
+endmenu
+
+endif
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/Makefile b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/Makefile
new file mode 100644
index 0000000..673ce8f
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-y			:= irq.o time.o mm.o devices.o
+
+# Board-specific support
+obj-$(CONFIG_MACH_UC7112LX)	+= board-UC-7112-LX.o
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/Makefile.boot b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/Makefile.boot
new file mode 100644
index 0000000..67039c3
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y	:= 0x00008000
+params_phys-y	:= 0x00000100
+initrd_phys-y	:= 0x00800000
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/board-UC-7112-LX.c b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/board-UC-7112-LX.c
new file mode 100644
index 0000000..124277e
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/board-UC-7112-LX.c
@@ -0,0 +1,42 @@
+/* Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com>
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/board.h>
+
+extern void moxart_init_irq(void);
+extern void moxart_map_io(void);
+extern void moxart_register_uart(void);
+extern void moxart_add_ethernet_devices(void);
+extern struct sys_timer moxart_timer;
+
+static void __init moxart_init(void)
+{
+	moxart_register_uart();
+	moxart_add_ethernet_devices();
+}
+
+static void __init fixup_uc711x(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi)
+{
+	//moxa_serial_init();
+}
+
+MACHINE_START(MOXART, "MOXA UC-7112-LX")
+	.fixup 			= fixup_uc711x,
+	.map_io			= moxart_map_io,
+	.init_machine	= moxart_init,
+	.init_irq		= moxart_init_irq,
+	.timer			= &moxart_timer,
+
+	//	.boot_params 	= 0x100,
+	//	.atag_offset	= 0x100,
+	//	.param_offset   = 0x00000100,
+MACHINE_END
+
+
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/devices.c b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/devices.c
new file mode 100644
index 0000000..740538f
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/devices.c
@@ -0,0 +1,152 @@
+/* Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com>
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/mtd/physmap.h>
+
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/board.h>
+
+static struct plat_serial8250_port __initdata serial_platform_data[] = {
+	{
+		.membase	= (void *)IO_ADDRESS(MOXART_UART1_BASE),
+		.mapbase	= MOXART_UART1_BASE,
+//		.iobase		= IO_ADDRESS(MOXART_UART1_BASE),
+		.irq		= IRQ_UART,
+		.uartclk	= UART_CLK,
+		.regshift	= 2,
+		.iotype		= UPIO_MEM,
+		.type		= PORT_16550A,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_FIXED_TYPE,
+	},
+	/*{
+		.membase	= (void *)IO_ADDRESS(MOXART_UART2_BASE),
+		.mapbase	= MOXART_UART2_BASE,
+//		.iobase		= IO_ADDRESS(MOXART_UART2_BASE),
+		.irq		= IRQ_UART,
+		.uartclk	= UART_CLK,
+		.regshift	= 2,
+		.iotype		= UPIO_MEM,
+		.type		= PORT_16550A,
+		.flags		= UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_FIXED_TYPE,
+	},*/
+	{},
+};
+
+static struct platform_device __initdata serial_device = {
+	.name	= "serial8250",
+	.id	= PLAT8250_DEV_PLATFORM,
+	.dev	= {
+		.platform_data = &serial_platform_data,
+	},
+};
+
+void __init moxart_register_uart(void)
+{
+	platform_device_register(&serial_device);
+}
+
+/*static struct uart_port moxart_serial_ports[] = {
+	{
+		.iobase		= IO_ADDRESS(MOXART_UART1_BASE),
+		.mapbase	= MOXART_UART1_BASE,
+		.irq		= IRQ_UART,
+		.flags		= UPF_SKIP_TEST | UPF_SHARE_IRQ,
+		.iotype		= UPIO_PORT,
+		.regshift	= 2,
+		.uartclk	= UART_CLK,
+		.line		= 0,
+		.type		= PORT_16550A,
+		.fifosize	= 16
+	},
+	{
+		.iobase		= IO_ADDRESS(MOXART_UART2_BASE),
+		.mapbase	= MOXART_UART2_BASE,
+		.irq		= IRQ_UART,
+		.flags		= UPF_SKIP_TEST | UPF_SHARE_IRQ,
+		.iotype		= UPIO_PORT,
+		.regshift	= 2,
+		.uartclk	= UART_CLK,
+		.line		= 1,
+		.type		= PORT_16550A,
+		.fifosize	= 16
+	}
+};*/
+
+/*static void __init moxart_serial_init(void)
+{
+    early_serial_setup(&moxart_serial_ports[0]);
+    early_serial_setup(&moxart_serial_ports[1]);
+}*/
+
+static struct resource __initdata moxart_mac1_resources[] = {
+	[0] = {
+		.start	= IO_ADDRESS(MOXART_FTMAC1_BASE),
+		.end	= IO_ADDRESS(MOXART_FTMAC1_BASE) + SZ_16K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_MAC1,
+		.end	= IRQ_MAC1,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct resource __initdata moxart_mac2_resources[] = {
+	[0] = {
+		.start	= IO_ADDRESS(MOXART_FTMAC2_BASE),
+		.end	= IO_ADDRESS(MOXART_FTMAC2_BASE) + SZ_16K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_MAC2,
+		.end	= IRQ_MAC2,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct moxart_eth_data __initdata moxart_mac1_data = {
+	.base_addr = IO_ADDRESS(MOXART_FTMAC1_BASE),
+	.irq = IRQ_MAC1,
+	.mac_addr_flash_offset = MOXART_FLASH_ETH1_OFFSET,
+};
+
+static struct moxart_eth_data __initdata moxart_mac2_data = {
+	.base_addr = IO_ADDRESS(MOXART_FTMAC2_BASE),
+	.irq = IRQ_MAC2,
+	.mac_addr_flash_offset = MOXART_FLASH_ETH2_OFFSET,
+};
+
+static struct platform_device __initdata moxart_mac1_device = {
+	.name		= "MOXART_RTL8201CP",
+	.id			= 0,
+	.dev		= {
+		.platform_data = &moxart_mac1_data,
+	},
+	.resource	= moxart_mac1_resources,
+	.num_resources	= ARRAY_SIZE(moxart_mac1_resources),
+};
+
+static struct platform_device __initdata moxart_mac2_device = {
+	.name		= "MOXART_RTL8201CP",
+	.id			= 1,
+	.dev		= {
+		.platform_data = &moxart_mac2_data,
+	},
+	.resource	= moxart_mac2_resources,
+	.num_resources	= ARRAY_SIZE(moxart_mac2_resources),
+};
+
+void __init moxart_add_ethernet_devices(struct moxart_eth_data *data)
+{
+	platform_device_register(&moxart_mac1_device);
+	platform_device_register(&moxart_mac2_device);
+}
+
+
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/board.h b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/board.h
new file mode 100644
index 0000000..a0f6d11
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/board.h
@@ -0,0 +1,25 @@
+/* Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com>
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
+ *
+ * These are data structures found in platform_device.dev.platform_data,
+ * and describing board-specific data needed by drivers.  For example,
+ * which pin is used for a given GPIO role.
+ *
+ * In 2.6, drivers should strongly avoid board-specific knowledge so
+ * that supporting new boards normally won't require driver patches.
+ * Most board-specific knowledge should be in arch/.../board-*.c files.
+ */
+
+#ifndef __ASM_ARCH_BOARD_H
+#define __ASM_ARCH_BOARD_H
+
+
+typedef struct moxart_eth_data {
+	unsigned int base_addr;
+	u8 mac_addr_flash_offset;
+	u8 irq;
+} moxart_eth_data_t;
+
+
+#endif
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/debug-macro.S b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/debug-macro.S
new file mode 100644
index 0000000..5be071c
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/debug-macro.S
@@ -0,0 +1,16 @@
+/* Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com>
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+#include <mach/hardware.h>
+
+	.macro	addruart,rx
+	mrc	p15, 0, \rx, c1, c0
+	tst	\rx, #1					@ MMU enabled?
+	ldreq	\rx, =MOXART_UART_BASE			@ physical
+	ldrne	\rx, =IO_ADDRESS(MOXART_UART_BASE)	@ virtual
+	.endm
+
+#define UART_SHIFT	2
+#define FLOW_CONTROL
+#include <asm/hardware/debug-8250.S>
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/entry-macro.S b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/entry-macro.S
new file mode 100644
index 0000000..c6a36e8
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/entry-macro.S
@@ -0,0 +1,44 @@
+/* Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com>
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+
+.macro  disable_fiq
+.endm
+
+.macro  get_irqnr_preamble, base, tmp
+.endm
+
+.macro  arch_ret_to_user, tmp1, tmp2
+.endm
+
+.macro get_fiqnr_and_base, irqnr, irqstat, base, tmp
+	ldr		\base, =(IO_ADDRESS(MOXART_INTERRUPT_BASE)+FIQ_STATUS_REG)
+	ldr		\irqstat, [\base]
+	mov		\irqnr, #32
+2001:           
+	tst		\irqstat, #1
+	bne		2002f
+	add		\irqnr, \irqnr, #1
+	mov		\irqstat, \irqstat, lsr #1
+	cmp		\irqnr, #64
+	bcc		2001b
+2002:           
+.endm
+
+.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+	ldr		\base, =(IO_ADDRESS(MOXART_INTERRUPT_BASE)+IRQ_STATUS_REG)
+	ldr		\irqstat, [\base]
+	mov		\irqnr, #0
+2003:           
+	tst		\irqstat, #1
+	bne		2004f
+	add		\irqnr, \irqnr, #1
+	mov		\irqstat, \irqstat, lsr #1
+	cmp		\irqnr, #32
+	bcc		2003b
+2004:           
+.endm
+
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/hardware.h b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/hardware.h
new file mode 100644
index 0000000..f3dc02a
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/hardware.h
@@ -0,0 +1,80 @@
+/* Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com>
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+#ifndef __MACH_HARDWARE_H
+#define __MACH_HARDWARE_H
+
+#define MOXART_AHB_BASE			0x90100000
+#define MOXART_UART_BASE		0x98200000
+#define MOXART_UART1_BASE		0x98200000
+#define MOXART_UART2_BASE		0x98200020
+#define MOXART_TIMER_BASE		0x98400000
+#define MOXART_TIMER1_BASE		MOXART_TIMER_BASE
+#define MOXART_TIMER2_BASE		(MOXART_TIMER_BASE + 0x10)
+#define MOXART_RTC_BASE			0x98600000
+#define MOXART_INTERRUPT_BASE	0x98800000
+#define MOXART_FLASH_BASE		0x80000000
+#define MOXART_FTMAC1_BASE		0x90900000
+#define MOXART_FTMAC2_BASE		0x92000000
+
+#define MOXART_WATCHDOG_BASE	0x98500000
+
+#define MOXART_FLASH_ETH1_OFFSET	0x50
+#define MOXART_FLASH_ETH2_OFFSET	0x56
+
+/*
+
+#define MOXART_GLOBAL_BASE		0x90100000
+#define MOXART_GLOBAL_BASE	0x90100000
+#define MOXART_POWER_CTRL_BASE	0x4B000000
+#define MOXART_GMAC0_BASE	0x6000A000
+#define MOXART_GMAC1_BASE	0x6000E000
+#define MOXART_FLASH_CTRL_BASE	0x65000000
+#define MOXART_DRAM_CTRL_BASE	0x66000000
+#define MOXART_GENERAL_DMA_BASE	0x67000000*/
+
+#define MOXART_FLASH_VA_BASE	0xf4000000
+
+#define UART_CLK	14745600 
+
+/*
+ * macro to get at IO space when running virtually
+ */
+
+/* #define IO_ADDRESS(x)	((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)*/
+
+#define IO_BASE	                        0xf0000000
+#define MEM_ADDRESS(x)                  ((x&0x0fffffff)+IO_BASE)
+#define IO_ADDRESS(x)                   (((x>>4)&0xffff0000)+(x&0xffff)+IO_BASE) 
+#define PHY_ADDRESS(x)                  (((x<<4)&0xfff00000)+(x&0xffff))
+
+/* Following is used Moxa CPU demo board
+ * Physical     Logical
+ * 90100000	f9010000	AHB controller
+ * 90200000	f9020000	SMC
+ * 90300000	f9030000	SDRAM controller
+ * 90400000	f9040000	DMA
+ * 90500000	f9050000	APB bridge
+ * 90900000	f9090000	MAC #1
+ * 90a00000	f90a0000	USB 2.0 host
+ * 90b00000	f90b0000	USB 2.0 device
+ * 90c00000	f90c0000	PCI bridge
+ * 90f00000	f90f0000	DES/3DES/AES encryptor
+ * 92000000	f9200000	MAC #2
+ * 92300000	f9230000	EBI
+ * 98100000	f9810000	PMU (power management)
+ * 98200000	f9820000	UART (port 1 - 6), embedded on CPU
+ * 98400000	f9840000	timer #1 & #2
+ * 98500000	f9850000	watchdog timer
+ * 98600000	f9860000	RTC, embedded on CPU
+ * 98700000	f9870000	GPIO
+ * 98800000	f9880000	INTC (interrupt controller)
+ * 98b00000	f98b0000	SPI
+ * 98e00000	f98e0000	SD controller
+ * 99400000	f9940000	AC97
+ * a0000000	a0000000	PCI memory
+ */
+
+
+#endif
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/io.h b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/io.h
new file mode 100644
index 0000000..dfd7f43
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/io.h
@@ -0,0 +1,13 @@
+/* Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com>
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+#ifndef __MACH_IO_H
+#define __MACH_IO_H
+
+#define IO_SPACE_LIMIT	0xffffffff
+
+#define __io(a)		__typesafe_io(a)
+#define __mem_pci(a)	(a)
+
+#endif /* __MACH_IO_H */
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/irqs.h b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/irqs.h
new file mode 100644
index 0000000..e5cd06e
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/irqs.h
@@ -0,0 +1,63 @@
+/* Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com>
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+#ifndef __MACH_IRQS_H__
+#define __MACH_IRQS_H__
+
+#define IRQ_UART	31
+#define IRQ_TIMER1	19
+#define IRQ_TIMER2	14
+#define IRQ_TIMER3	15
+#define IRQ_MAC1	25
+#define IRQ_MAC2	27
+
+/*
+ #define IRQ_SERIRQ1	11
+ #define IRQ_SERIRQ0	10
+ #define IRQ_PWR		26
+ #define IRQ_CIR		25
+ #define IRQ_RTC		17
+ #define IRQ_FLASH	12
+ #define IRQ_DMA		9
+ #define IRQ_WATCHDOG	3
+ #define IRQ_IPI		0
+ */
+
+#define MOXART_NR_IRQS		32
+#define MOXART_NR_FIQS		32
+#define NR_IRQS				(MOXART_NR_IRQS + MOXART_NR_FIQS + 16)
+
+#define LEVEL				0
+#define EDGE				1
+#define H_ACTIVE			0
+#define L_ACTIVE			1
+
+#define IRQ_SOURCE_REG		0
+#define IRQ_MASK_REG		0x04
+#define IRQ_CLEAR_REG		0x08
+#define IRQ_MODE_REG		0x0c
+#define IRQ_LEVEL_REG		0x10
+#define IRQ_STATUS_REG		0x14
+
+#define FIQ_SOURCE_REG		0x20
+#define FIQ_MASK_REG		0x24
+#define FIQ_CLEAR_REG		0x28
+#define FIQ_MODE_REG		0x2c
+#define FIQ_LEVEL_REG		0x30
+#define FIQ_STATUS_REG		0x34
+
+#define IRQ_SOURCE(base_addr)	(base_addr + 0x00)
+#define IRQ_MASK(base_addr)		(base_addr + 0x04)
+#define IRQ_CLEAR(base_addr)	(base_addr + 0x08)
+#define IRQ_TMODE(base_addr)	(base_addr + 0x0C)
+#define IRQ_TLEVEL(base_addr)	(base_addr + 0x10)
+#define IRQ_STATUS(base_addr)	(base_addr + 0x14)
+#define FIQ_SOURCE(base_addr)	(base_addr + 0x20)
+#define FIQ_MASK(base_addr)		(base_addr + 0x24)
+#define FIQ_CLEAR(base_addr)	(base_addr + 0x28)
+#define FIQ_TMODE(base_addr)	(base_addr + 0x2C)
+#define FIQ_TLEVEL(base_addr)	(base_addr + 0x30)
+#define FIQ_STATUS(base_addr)	(base_addr + 0x34)
+
+#endif /* __MACH_IRQS_H__ */
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/memory.h b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/memory.h
new file mode 100644
index 0000000..bd1e0c7
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/memory.h
@@ -0,0 +1,15 @@
+/* Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com>
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+#ifndef __MACH_MEMORY_H
+#define __MACH_MEMORY_H
+
+#define DRAM_BASE       0x00000000
+#define DRAM_SIZE       SZ_32M
+#define MEM_SIZE        DRAM_SIZE
+
+#define PHYS_OFFSET     UL(DRAM_BASE)
+#define END_MEM         (DRAM_BASE + DRAM_SIZE)
+
+#endif /* __MACH_MEMORY_H */
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/serial.h b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/serial.h
new file mode 100644
index 0000000..1b94154
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/serial.h
@@ -0,0 +1,19 @@
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+/*
+ * This assumes you have a 3.6864 MHz clock for your UART.
+ */
+#define BASE_BAUD (CONFIG_UART_CLK / 16)
+
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) 
+
+#define STD_SERIAL_PORT_DEFNS       \
+    /* MAGIC UART CLK   PORT       IRQ     FLAGS */        \
+    { 0, BASE_BAUD, MOXART_UART1_BASE, IRQ_UART, STD_COM_FLAGS },   \
+    { 0, BASE_BAUD, MOXART_UART2_BASE, IRQ_UART, STD_COM_FLAGS },   \
+
+#define EXTRA_SERIAL_PORT_DEFNS
+
+#endif
+
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/system.h b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/system.h
new file mode 100644
index 0000000..22c0f55
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/system.h
@@ -0,0 +1,46 @@
+/* Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com>
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+#ifndef __MACH_SYSTEM_H
+#define __MACH_SYSTEM_H
+
+#include <linux/io.h>
+#include <mach/hardware.h>
+
+static inline void arch_idle(void)
+{
+	/*
+	 * Because of broken hardware we have to enable interrupts or the CPU
+	 * will never wakeup... Acctualy it is not very good to enable
+	 * interrupts here since scheduler can miss a tick, but there is
+	 * no other way around this. Platforms that needs it for power saving
+	 * should call enable_hlt() in init code, since by default it is
+	 * disabled.
+	 */
+	local_irq_enable();
+	cpu_do_idle();
+}
+
+
+/*
+#define RESET_GLOBAL		(1 << 31)
+#define RESET_CPU1			(1 << 30)
+#define GLOBAL_RESET		0x0C
+*/
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+	//__raw_writel(RESET_GLOBAL | RESET_CPU1, IO_ADDRESS(MOXART_GLOBAL_BASE) + GLOBAL_RESET);
+
+	if ( mode == 's' ) {	// Jump to ROM address 0
+		cpu_reset(0);
+	}
+	else {					// reset the CPU
+		__raw_writel(1, 		IO_ADDRESS(MOXART_WATCHDOG_BASE)+4);		// set counter to 1
+		__raw_writel(0x5ab9, 	IO_ADDRESS(MOXART_WATCHDOG_BASE)+8); 		// start the watch dog
+		__raw_writel(0x03, 		IO_ADDRESS(MOXART_WATCHDOG_BASE)+12);		// set to reset the CPU
+	}
+}
+
+#endif /* __MACH_SYSTEM_H */
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/timex.h b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/timex.h
new file mode 100644
index 0000000..56d6928
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/timex.h
@@ -0,0 +1,5 @@
+/* Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com>
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+#define CLOCK_TICK_RATE 33000000
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/uncompress.h b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/uncompress.h
new file mode 100644
index 0000000..c7cf462
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/uncompress.h
@@ -0,0 +1,34 @@
+/* Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com>
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#include <linux/serial_reg.h>
+#include <mach/hardware.h>
+
+static volatile unsigned long *UART = (unsigned long *)MOXART_UART_BASE;
+
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ */
+static inline void putc(char c)
+{
+	while (!(UART[UART_LSR] & UART_LSR_THRE))
+		barrier();
+	UART[UART_TX] = c;
+}
+
+#define flush() do { } while (0)
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
+
+#endif /* __MACH_UNCOMPRESS_H */
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/vmalloc.h b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/vmalloc.h
new file mode 100644
index 0000000..8b0e2b4
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/include/mach/vmalloc.h
@@ -0,0 +1,7 @@
+/* Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com>
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+/*#define VMALLOC_END	0xF0000000*/
+
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/irq.c b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/irq.c
new file mode 100644
index 0000000..e9403cd
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/irq.c
@@ -0,0 +1,129 @@
+/* Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com>
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/stddef.h>
+#include <linux/list.h>
+#include <linux/sched.h>
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+
+static void moxart_ack_irq(unsigned int irq)
+{
+	if (irq < 32) {
+		__raw_writel(1 << irq, IRQ_CLEAR(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+	}
+	if (irq < 64) {
+		irq -= 32;
+		__raw_writel(1 << irq, FIQ_CLEAR(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+	}
+}
+
+static void moxart_mask_irq(unsigned int irq)
+{
+	unsigned int mask;
+	if (irq < 32) {
+		mask = __raw_readl(IRQ_MASK(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+		mask &= ~(1 << irq);
+		__raw_writel(mask, IRQ_MASK(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+	}
+	if (irq < 64) {
+		irq -= 32;
+		mask = __raw_readl(FIQ_MASK(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+		mask &= ~(1 << irq);
+		__raw_writel(mask, FIQ_MASK(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+	}
+}
+
+static void moxart_unmask_irq(unsigned int irq)
+{
+	unsigned int mask;
+	if (irq < 32) {
+		mask = __raw_readl(IRQ_MASK(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+		mask |= (1 << irq);
+		__raw_writel(mask, IRQ_MASK(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+	}
+	if (irq < 64) {
+		irq -= 32;
+		mask = __raw_readl(FIQ_MASK(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+		mask |= (1 << irq);
+		__raw_writel(mask, FIQ_MASK(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+	}
+}
+
+void moxart_generic_set_generic(unsigned int base, unsigned int irq, unsigned int low)
+{
+    unsigned int mask;
+    mask = __raw_readl(base);
+    ( low ) ? ( mask |= (1 << irq) ) : ( mask &= ~(1 << irq) );
+    __raw_writel(mask, base);
+}
+
+/*void __init moxart_int_set_irq(unsigned int irq, int mode, int level)*/
+void moxart_int_set_irq(unsigned int irq, int mode, int level)
+{
+    if (irq < 32) {
+        moxart_generic_set_generic(IRQ_TMODE(IO_ADDRESS(MOXART_INTERRUPT_BASE)), irq, mode);
+        moxart_generic_set_generic(IRQ_TLEVEL(IO_ADDRESS(MOXART_INTERRUPT_BASE)), irq, level);
+    }
+    if (irq < 64) {
+        irq -= 32;
+        moxart_generic_set_generic(FIQ_TMODE(IO_ADDRESS(MOXART_INTERRUPT_BASE)), irq, mode);
+        moxart_generic_set_generic(FIQ_TLEVEL(IO_ADDRESS(MOXART_INTERRUPT_BASE)), irq, level);
+    }
+}
+
+static struct irq_chip moxart_irq_chip = {
+	.name	= "INTC",
+	.ack	= moxart_ack_irq,
+	.mask	= moxart_mask_irq,
+	.unmask	= moxart_unmask_irq,
+};
+
+static struct resource irq_resource = {
+	.name	= "irq_handler",
+	.start	= IO_ADDRESS(MOXART_INTERRUPT_BASE),
+	.end	= IO_ADDRESS(FIQ_STATUS(MOXART_INTERRUPT_BASE)) + 4,
+};
+
+void __init moxart_init_irq(void)
+{
+	unsigned int mode = 0, level = 0, irq;
+
+	disable_hlt();
+
+	request_resource(&iomem_resource, &irq_resource);
+
+	for (irq = 0; irq < NR_IRQS; irq++) {
+		set_irq_chip(irq, &moxart_irq_chip);
+		if(irq == IRQ_TIMER1 || irq == IRQ_TIMER2 || irq == IRQ_TIMER3 /*|| irq == 31*/) {
+			set_irq_handler(irq, handle_edge_irq);
+			mode |= (1 << irq);
+			level |= (1 << irq);
+		}
+		else {
+			set_irq_handler(irq, handle_level_irq);
+		}
+		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+	}
+	//printk("IRQ chip/handler/flags assign finished\r\n");
+
+	__raw_writel(0, IRQ_MASK(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+	__raw_writel(0, FIQ_MASK(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+
+	__raw_writel(0xffffffff, IRQ_CLEAR(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+	__raw_writel(0xffffffff, FIQ_CLEAR(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+	//printk("IRQ init finished\n");
+
+	__raw_writel(mode, IRQ_TMODE(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+	__raw_writel(level, IRQ_TLEVEL(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+	__raw_writel(0, FIQ_TMODE(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+	__raw_writel(0, FIQ_TLEVEL(IO_ADDRESS(MOXART_INTERRUPT_BASE)));
+	//printk("IRQ mode/level setup finished\n");
+
+	printk("MOXART CPU IRQ: init_irq finished\n");
+}
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/mm.c b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/mm.c
new file mode 100644
index 0000000..1891b1d
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/mm.c
@@ -0,0 +1,70 @@
+/* Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com>
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+
+/* Page table mapping for I/O region */
+static struct map_desc moxart_io_desc[] __initdata = {
+	{
+		.virtual	= IO_ADDRESS(MOXART_AHB_BASE),
+		.pfn		=__phys_to_pfn(MOXART_AHB_BASE),
+		.length		= SZ_4K,
+		.type 		= MT_DEVICE,
+	}, {
+		.virtual	= IO_ADDRESS(MOXART_TIMER_BASE),
+		.pfn		= __phys_to_pfn(MOXART_TIMER_BASE),
+		.length		= SZ_4K,
+		.type 		= MT_DEVICE,
+    }, {
+		.virtual	= IO_ADDRESS(MOXART_RTC_BASE),
+		.pfn		= __phys_to_pfn(MOXART_RTC_BASE),
+		.length		= SZ_4K,
+		.type 		= MT_DEVICE,
+	}, {
+        .virtual    = IO_ADDRESS(MOXART_UART1_BASE),
+        .pfn        = __phys_to_pfn(MOXART_UART1_BASE),
+        .length     = SZ_4K,
+        .type       = MT_DEVICE,
+	}, {
+        .virtual    = IO_ADDRESS(MOXART_UART2_BASE),
+        .pfn        = __phys_to_pfn(MOXART_UART2_BASE),
+        .length     = SZ_4K,
+        .type       = MT_DEVICE,
+	}, {
+		.virtual    = IO_ADDRESS(MOXART_INTERRUPT_BASE),
+		.pfn        = __phys_to_pfn(MOXART_INTERRUPT_BASE),
+		.length     = SZ_4K,
+		.type       = MT_DEVICE,
+	}, {
+		.virtual    = IO_ADDRESS(MOXART_FTMAC1_BASE),
+		.pfn        = __phys_to_pfn(MOXART_FTMAC1_BASE),
+		.length     = SZ_4K,
+		.type       = MT_DEVICE,
+	}, {
+		.virtual    = IO_ADDRESS(MOXART_FTMAC2_BASE),
+		.pfn        = __phys_to_pfn(MOXART_FTMAC2_BASE),
+		.length     = SZ_4K,
+		.type       = MT_DEVICE,
+	}, {
+		.virtual    = IO_ADDRESS(MOXART_WATCHDOG_BASE),
+		.pfn        = __phys_to_pfn(MOXART_WATCHDOG_BASE),
+		.length     = SZ_4K,
+		.type       = MT_DEVICE,
+	}, {
+		.virtual    = IO_ADDRESS(MOXART_FLASH_BASE),
+		.pfn        = __phys_to_pfn(MOXART_FLASH_BASE),
+		.length     = SZ_16M,
+		.type       = MT_DEVICE,
+    }
+};
+
+void __init moxart_map_io(void)
+{
+    iotable_init(moxart_io_desc, ARRAY_SIZE(moxart_io_desc));
+}
diff --git a/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/time.c b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/time.c
new file mode 100644
index 0000000..700eeb9
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/mach-moxart/time.c
@@ -0,0 +1,139 @@
+/* Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com>
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <mach/hardware.h>
+#include <asm/mach/time.h>
+
+#define TIMER_1_COUNT(base_addr)		(base_addr + 0x00)
+#define TIMER_1_LOAD(base_addr)			(base_addr + 0x04)
+#define TIMER_1_MATCH1(base_addr)		(base_addr + 0x08)
+#define TIMER_1_MATCH2(base_addr)		(base_addr + 0x0C)
+
+#define TIMER_2_COUNT(base_addr)		(base_addr + 0x10)
+#define TIMER_2_LOAD(base_addr)			(base_addr + 0x14)
+#define TIMER_2_MATCH1(base_addr)		(base_addr + 0x18)
+#define TIMER_2_MATCH2(base_addr)		(base_addr + 0x1C)
+
+#define TIMER_3_COUNT(base_addr)		(base_addr + 0x20)
+#define TIMER_3_LOAD(base_addr)			(base_addr + 0x24)
+#define TIMER_3_MATCH1(base_addr)		(base_addr + 0x28)
+#define TIMER_3_MATCH2(base_addr)		(base_addr + 0x2C)
+
+#define TIMER_CR(base_addr)				(base_addr + 0x30)
+
+#define TIMER_1_CR_ENABLE(base_addr)	(base_addr + 0x30)
+#define TIMER_1_CR_EXTCLK(base_addr)	(base_addr + 0x34)
+#define TIMER_1_CR_FLOWIN(base_addr)	(base_addr + 0x38)
+
+#define TIMER_2_CR_ENABLE(base_addr)	(base_addr + 0x42)
+#define TIMER_2_CR_EXTCLK(base_addr)	(base_addr + 0x46)
+#define TIMER_2_CR_FLOWIN(base_addr)	(base_addr + 0x50)
+
+#define TIMER_3_CR_ENABLE(base_addr)	(base_addr + 0x54)
+#define TIMER_3_CR_EXTCLK(base_addr)	(base_addr + 0x58)
+#define TIMER_3_CR_FLOWIN(base_addr)	(base_addr + 0x62)
+
+#define TIMER_INTR_STATE(base_addr)		(base_addr + 0x34)
+
+#define TIMEREG_1_CR_ENABLE			(1 << 0)
+#define TIMEREG_1_CR_CLOCK			(1 << 1)
+#define TIMEREG_1_CR_INT			(1 << 2)
+#define TIMEREG_2_CR_ENABLE			(1 << 3)
+#define TIMEREG_2_CR_CLOCK			(1 << 4)
+#define TIMEREG_2_CR_INT			(1 << 5)
+#define TIMEREG_3_CR_ENABLE			(1 << 6)
+#define TIMEREG_3_CR_CLOCK			(1 << 7)
+#define TIMEREG_3_CR_INT			(1 << 8)
+#define TIMEREG_COUNT_UP			(1 << 9)
+#define TIMEREG_COUNT_DOWN			(0 << 9)
+
+#define APB_CLK		48000000
+#define MAX_TIMER	2
+#define USED_TIMER	1
+
+#define TIMER1_COUNT                0x0
+#define TIMER1_LOAD                 0x4
+#define TIMER1_MATCH1               0x8
+#define TIMER1_MATCH2               0xC
+#define TIMER2_COUNT                0x10
+#define TIMER2_LOAD                 0x14
+#define TIMER2_MATCH1               0x18
+#define TIMER2_MATCH2               0x1C
+#define TIMER3_COUNT                0x20
+#define TIMER3_LOAD                 0x24
+#define TIMER3_MATCH1               0x28
+#define TIMER3_MATCH2               0x2C 
+#define TIMER_INTR_MASK		0x38
+
+static irqreturn_t moxart_timer_interrupt(int irq, void *dev_id)
+{
+	// printk("TIMER moxart_timer_interrupt irq = %d\n", irq);
+	// __raw_writel(0, TIMER_INTR_STATE(IO_ADDRESS(MOXART_TIMER1_BASE)));
+
+	timer_tick();
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction moxart_timer_irq = {
+	.name		= "MOXART Timer Tick",
+	.flags		= IRQF_DISABLED | IRQF_TIMER,
+	.handler	= moxart_timer_interrupt,
+};
+
+static struct resource timer_resource = {
+	.name	= "timer_handler",
+	.start	= IO_ADDRESS(MOXART_TIMER_BASE),
+	.end	= IO_ADDRESS(TIMER_INTR_STATE(MOXART_TIMER_BASE)) + 4,
+};
+
+void __init moxart_timer_init(void)
+{
+	unsigned int t_int;
+
+	setup_irq(IRQ_TIMER1, &moxart_timer_irq);
+
+	/*t_int = __raw_readl(TIMER_INTR_STATE(IO_ADDRESS(MOXART_TIMER1_BASE)));
+	printk("TIMER TIMER_INTR_STATE(IO_ADDRESS(MOXART_TIMER1_BASE)) = %d\n", t_int);
+	t_int = __raw_readl(TIMER_1_COUNT(IO_ADDRESS(MOXART_TIMER1_BASE)));
+	printk("TIMER TIMER_1_COUNT(IO_ADDRESS(MOXART_TIMER1_BASE)) = %d\n", t_int);*/
+
+	__raw_writel(APB_CLK / HZ, TIMER_1_COUNT(IO_ADDRESS(MOXART_TIMER_BASE)));
+	__raw_writel(APB_CLK / HZ, TIMER_1_LOAD(IO_ADDRESS(MOXART_TIMER_BASE)));
+
+	/*
+	__raw_writel(0xffffffff, TIMER_1_MATCH1(IO_ADDRESS(MOXART_TIMER_BASE)));
+	__raw_writel(0xffffffff, TIMER_1_MATCH2(IO_ADDRESS(MOXART_TIMER_BASE)));
+	*/
+
+	//__raw_writel(TIMER_1_CR_ENABLE | TIMER_1_CR_INT, TIMER_CR(IO_ADDRESS(MOXART_TIMER1_BASE)));
+	//__raw_writel((1 << 0) | (1 << 2), TIMER_1_CR_ENABLE(IO_ADDRESS(MOXART_TIMER_BASE)));
+	//__raw_writel(0x0000020f, TIMER_1_CR_ENABLE(IO_ADDRESS(MOXART_TIMER_BASE)));
+	//__raw_writel(TIMEREG_COUNT_UP | TIMEREG_1_CR_ENABLE | TIMEREG_1_CR_INT | TIMEREG_1_CR_CLOCK, TIMER_1_CR_ENABLE(IO_ADDRESS(MOXART_TIMER_BASE)));
+	//__raw_writel(TIMEREG_COUNT_UP | TIMEREG_1_CR_ENABLE | TIMEREG_1_CR_INT, TIMER_1_CR_ENABLE(IO_ADDRESS(MOXART_TIMER_BASE)));
+
+	__raw_writel(1, TIMER_1_CR_ENABLE(IO_ADDRESS(MOXART_TIMER_BASE)));
+	__raw_writel(0, TIMER_1_CR_EXTCLK(IO_ADDRESS(MOXART_TIMER_BASE)));
+	__raw_writel(1, TIMER_1_CR_FLOWIN(IO_ADDRESS(MOXART_TIMER_BASE)));
+
+	/*t_int = __raw_readl(TIMER_INTR_STATE(IO_ADDRESS(MOXART_TIMER1_BASE)));
+	printk("TIMER TIMER_INTR_STATE(IO_ADDRESS(MOXART_TIMER1_BASE)) = %d\n", t_int);
+
+	t_int = __raw_readl(TIMER_1_COUNT(IO_ADDRESS(MOXART_TIMER1_BASE)));
+	printk("TIMER TIMER_1_COUNT(IO_ADDRESS(MOXART_TIMER1_BASE)) = %d\n", t_int);
+	t_int = __raw_readl(TIMER_1_LOAD(IO_ADDRESS(MOXART_TIMER1_BASE)));
+	printk("TIMER TIMER_1_LOAD(IO_ADDRESS(MOXART_TIMER1_BASE)) = %d\n", t_int);
+	*/
+
+	printk("MOXART CPU TIMER: timer count/load set (APB_CLK / HZ) where APB_CLK=%d HZ=%d IRQ=0x%x\n", APB_CLK, HZ, IRQ_TIMER1);
+}
+
+struct sys_timer moxart_timer = {
+    .init       = moxart_timer_init,
+};
+
diff --git a/tmp/linux-2.6.32.60/arch/arm/tools/mach-types b/linux-2.6.32.60-mach-moxart/arch/arm/tools/mach-types
index 07b976d..0aac27e 100644
--- a/tmp/linux-2.6.32.60/arch/arm/tools/mach-types
+++ b/linux-2.6.32.60-mach-moxart/arch/arm/tools/mach-types
@@ -2536,3 +2536,4 @@ c3ax03			MACH_C3AX03		C3AX03			2549
 mxt_td60		MACH_MXT_TD60		MXT_TD60		2550
 esyx			MACH_ESYX		ESYX			2551
 bulldog			MACH_BULLDOG		BULLDOG			2553
+moxart			MACH_UC7112LX		MOXART			5000
diff --git a/tmp/linux-2.6.32.60/drivers/mtd/maps/Kconfig b/linux-2.6.32.60-mach-moxart/drivers/mtd/maps/Kconfig
index 14be075..95bf6e3 100644
--- a/tmp/linux-2.6.32.60/drivers/mtd/maps/Kconfig
+++ b/linux-2.6.32.60-mach-moxart/drivers/mtd/maps/Kconfig
@@ -253,6 +253,12 @@ config MTD_NETtel
 	help
 	  Support for flash chips on NETtel/SecureEdge/SnapGear boards.
 
+config MTD_UC7112LX
+    tristate "CFI Flash device mapped on MOXART UC_7112_LX_PLUS"
+    depends on ARM && MTD_CFI && MTD_COMPLEX_MAPPINGS
+    help
+      This enables MTD access to flash device on MOXA UC-7112-LX.
+
 config MTD_ALCHEMY
 	tristate "AMD Alchemy Pb1xxx/Db1xxx/RDK MTD support"
 	depends on SOC_AU1X00 && MTD_PARTITIONS && MTD_CFI
diff --git a/tmp/linux-2.6.32.60/drivers/mtd/maps/Makefile b/linux-2.6.32.60-mach-moxart/drivers/mtd/maps/Makefile
index ae2f6db..e599d6f 100644
--- a/tmp/linux-2.6.32.60/drivers/mtd/maps/Makefile
+++ b/linux-2.6.32.60-mach-moxart/drivers/mtd/maps/Makefile
@@ -61,3 +61,4 @@ obj-$(CONFIG_MTD_BFIN_ASYNC)	+= bfin-async-flash.o
 obj-$(CONFIG_MTD_RBTX4939)	+= rbtx4939-flash.o
 obj-$(CONFIG_MTD_VMU)		+= vmu-flash.o
 obj-$(CONFIG_MTD_GPIO_ADDR)	+= gpio-addr-flash.o
+obj-$(CONFIG_MTD_UC7112LX)    += uc7112lx.o
diff --git a/linux-2.6.32.60-mach-moxart/drivers/mtd/maps/uc7112lx.c b/linux-2.6.32.60-mach-moxart/drivers/mtd/maps/uc7112lx.c
new file mode 100644
index 0000000..0c95c89
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/drivers/mtd/maps/uc7112lx.c
@@ -0,0 +1,143 @@
+/* UC-7112-LX flash mapping driver
+ * Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com> ( based on MOXA sources modified for 2.6.32.60 )
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+#include <mach/hardware.h>
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/io.h>
+
+#define RW_PART0_OF	0x0
+#define RW_PART0_SZ	0x40000						// bootloader for MOXART CPU
+
+#define RW_PART1_OF	(RW_PART0_OF+RW_PART0_SZ)
+#define RW_PART1_SZ	(0x200000-RW_PART0_SZ)		// kernel
+
+#define RW_PART2_OF	(RW_PART1_OF+RW_PART1_SZ)
+#define RW_PART2_SZ	0x800000					// root fs
+
+#define RW_PART3_OF	(RW_PART2_OF+RW_PART2_SZ)
+#define RW_PART3_SZ	0x600000					// user fs
+
+#define CONFIG_FLASH_MEM_BASE 0x80000000
+#define CONFIG_FLASH_SIZE 0x01000000
+
+static struct map_info moxart_flash_map = {
+	.name       = "UC-7112-LX-PLUS",
+	.bankwidth  = 2,
+	.phys       = CONFIG_FLASH_MEM_BASE,
+	.size       = CONFIG_FLASH_SIZE,
+	.virt       = (void __iomem *)IO_ADDRESS(CONFIG_FLASH_MEM_BASE),
+//	.virt		= 0xf4000000, // MTD: Unable to init map for flash
+};
+
+static struct mtd_partition moxart_flash_partitions[] = {
+	{
+		.name = "Bootloader",
+		.offset = RW_PART0_OF,
+		.size = RW_PART0_SZ
+	},
+	{
+		.name = "LinuxKernel",
+		.offset = RW_PART1_OF,
+		.size = RW_PART1_SZ,
+		//.mask_flags = MTD_WRITEABLE
+	},
+	{
+		.name = "RootFileSystem",
+		.offset = RW_PART2_OF,
+		.size = RW_PART2_SZ,
+	//	.mask_flags = MTD_WRITEABLE
+	},
+	{
+		.name = "UserDisk",
+		.offset = RW_PART3_OF,
+		.size = RW_PART3_SZ
+	}
+};
+
+/*struct map_info moxart_flash_map = {
+	.name = "UC7110LX V2 FLASH",
+	.size = CONFIG_FLASH_SIZE,
+	.bankwidth = 2,
+	.phys = CONFIG_FLASH_MEM_BASE,
+	.virt = IO_ADDRESS(CONFIG_FLASH_MEM_BASE),
+};
+
+static int mtd_reboot(struct notifier_block *n, unsigned long code, void *p)
+{      
+	if(code != SYS_RESTART)
+				return NOTIFY_DONE;
+   
+	*( u16 *)(IO_ADDRESS(CONFIG_FLASH_MEM_BASE) + (0x55 * 2)) = 0xb0;
+	*( u16 *)(IO_ADDRESS(CONFIG_FLASH_MEM_BASE) + (0x55 * 2)) = 0xff;
+		return NOTIFY_DONE;
+}
+
+static struct notifier_block mtd_notifier = {
+	notifier_call:  mtd_reboot,
+	next:           NULL,
+	priority:       0
+};*/
+
+static struct mtd_info *moxart_mtd;
+
+int __init init_flash(void)
+{
+	
+	printk(KERN_NOTICE "MTD: MOXART CPU flash: probing %d-bit flash bus, flash mapping: 0x%x at 0x%x\n", moxart_flash_map.bankwidth*8, CONFIG_FLASH_SIZE, CONFIG_FLASH_MEM_BASE);
+	simple_map_init(&moxart_flash_map);
+
+	moxart_mtd = do_map_probe("cfi_probe",&moxart_flash_map);
+	if (moxart_mtd) {
+		moxart_mtd->owner = THIS_MODULE;
+		printk(KERN_NOTICE "MTD: Using static partition definition\n");	
+		add_mtd_partitions(moxart_mtd, moxart_flash_partitions, ARRAY_SIZE(moxart_flash_partitions));
+	} else {
+		printk(KERN_ERR "MTD: map probe failed for flash\n");
+		iounmap(moxart_flash_map.virt);		
+		return -ENXIO;
+	}
+
+	//return -ENXIO;
+	return 0;
+}
+
+int __init init_moxart_flash(void)
+{   
+	int status;
+
+	if ((status = init_flash())) {
+		printk(KERN_ERR "MTD: Unable to init map for flash\n");
+	} else {
+		//register_reboot_notifier(&mtd_notifier);
+	}
+	return status;
+}
+
+
+static void __exit cleanup_moxart_flash(void)
+{
+	if (moxart_mtd) {
+		//unregister_reboot_notifier(&mtd_notifier);
+		del_mtd_partitions(moxart_mtd);
+		map_destroy(moxart_mtd);
+	}
+}
+
+module_init(init_moxart_flash);
+module_exit(cleanup_moxart_flash);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jonas Jensen");
+MODULE_DESCRIPTION("MTD map driver for UC-7112-LX");
diff --git a/tmp/linux-2.6.32.60/drivers/net/arm/Kconfig b/linux-2.6.32.60-mach-moxart/drivers/net/arm/Kconfig
index c37ee9e..bbe4041 100644
--- a/tmp/linux-2.6.32.60/drivers/net/arm/Kconfig
+++ b/linux-2.6.32.60-mach-moxart/drivers/net/arm/Kconfig
@@ -71,3 +71,10 @@ config W90P910_ETH
 	help
 	  Say Y here if you want to use built-in Ethernet ports
 	  on w90p910 processor.
+	  
+config MOXART_ETHER
+	bool "MOXART SoC Ethernet support"
+	depends on ARCH_MOXART
+	help
+	  Say Y here if you want to use built-in MOXART SoC Ethernet ports
+
diff --git a/tmp/linux-2.6.32.60/drivers/net/arm/Makefile b/linux-2.6.32.60-mach-moxart/drivers/net/arm/Makefile
index 303171f..bf6a1c2 100644
--- a/tmp/linux-2.6.32.60/drivers/net/arm/Makefile
+++ b/linux-2.6.32.60-mach-moxart/drivers/net/arm/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_ARM_KS8695_ETHER)	+= ks8695net.o
 obj-$(CONFIG_EP93XX_ETH)	+= ep93xx_eth.o
 obj-$(CONFIG_IXP4XX_ETH)	+= ixp4xx_eth.o
 obj-$(CONFIG_W90P910_ETH)	+= w90p910_ether.o
+obj-$(CONFIG_MOXART_ETHER)		+= moxart_ether.o
diff --git a/linux-2.6.32.60-mach-moxart/drivers/net/arm/moxart_ether.c b/linux-2.6.32.60-mach-moxart/drivers/net/arm/moxart_ether.c
new file mode 100644
index 0000000..ae595f3
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/drivers/net/arm/moxart_ether.c
@@ -0,0 +1,472 @@
+/* MOXART Ethernet (RTL8201CP) Device Driver
+ * Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com> ( based on MOXA sources modified for 2.6.32.60 )
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/dma-mapping.h>
+#include <linux/ethtool.h>
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+#include <mach/board.h>
+
+#include "moxart_ether.h"
+
+#define DRV_NAME	"moxart_ether"
+#define DRV_VERSION	"1.0"
+
+static inline unsigned long moxart_emac_read(struct net_device *dev, unsigned int reg)
+{
+	void __iomem *emac_base = (void __iomem *)dev->base_addr;
+	return __raw_readl(emac_base + reg);
+}
+
+static inline void moxart_emac_write(struct net_device *dev, unsigned int reg, unsigned long value )
+{
+	void __iomem *emac_base = (void __iomem *)dev->base_addr;
+	__raw_writel(value, emac_base + reg);
+}
+
+static void __init moxart_get_mac_address(struct net_device *dev, u8 mac_addr_flash_offset) // Get MAC address stored in flash memory and write it to net_device
+{
+	int i;
+	for (i=0; i <= 5; i++) dev->dev_addr[i] = inb(IO_ADDRESS(MOXART_FLASH_BASE) + mac_addr_flash_offset + i);
+	dbg_printk("MOXART Ethernet: finished get_mac_address dev->base_addr=%x\n", (unsigned int) dev->base_addr);
+}
+
+static void moxart_update_mac_address(struct net_device *dev) // Program the hardware MAC address from dev->dev_addr
+{
+	moxart_emac_write(dev, MAC_MADR_REG_OFFSET, ( (dev->dev_addr[0] << 8) | (dev->dev_addr[1]) ) );
+	moxart_emac_write(dev, MAC_MADR_REG_OFFSET + 4, ( (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) | (dev->dev_addr[4] << 8) | (dev->dev_addr[5]) ) );
+	dbg_printk("MOXART Ethernet: finished moxart_update_mac_address dev->base_addr=%x MAC=%x%x\n", (unsigned int) dev->base_addr, __raw_readl(dev->base_addr + MAC_MADR_REG_OFFSET), __raw_readl(dev->base_addr + MAC_MADR_REG_OFFSET + 4) );
+}
+
+static int moxart_set_mac_address(struct net_device *dev, void* addr)
+{
+	struct sockaddr *address = addr;
+
+	if (!is_valid_ether_addr(address->sa_data))	{
+		return -EADDRNOTAVAIL;
+	}
+
+	memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
+	moxart_update_mac_address(dev);
+
+	dbg_printk("MOXART Ethernet: finished moxart_set_mac_address dev->base_addr=%x\n", (unsigned int) dev->base_addr);
+	return 0;
+}
+
+static void moxart_mac_free_memory(struct net_device *dev)
+{
+	moxart_mac_priv_t *priv = netdev_priv(dev);
+	if ( priv->virtTxDescBaseAddr )
+		dma_free_coherent(NULL, sizeof(tx_desc_t)*TX_DESC_NUM, priv->virtTxDescBaseAddr, priv->phyTxDescBaseAddr);
+	if ( priv->virtRxDescBaseAddr )
+		dma_free_coherent(NULL, sizeof(rx_desc_t)*RX_DESC_NUM, priv->virtRxDescBaseAddr, priv->phyRxDescBaseAddr);
+	if ( priv->virtTxBufBaseAddr )
+		dma_free_coherent(NULL, TX_BUF_SIZE*TX_DESC_NUM, priv->virtTxBufBaseAddr, priv->phyTxBufBaseAddr);
+	if ( priv->virtRxBufBaseAddr )
+		dma_free_coherent(NULL, RX_BUF_SIZE*RX_DESC_NUM, priv->virtRxBufBaseAddr, priv->phyRxBufBaseAddr);
+}
+
+static void moxart_mac_reset(struct net_device *dev)
+{
+	moxart_mac_priv_t *priv = netdev_priv(dev);
+	outl(SW_RST, dev->base_addr + MACCR_REG_OFFSET);
+	while (inl(dev->base_addr + MACCR_REG_OFFSET) & SW_RST) {
+		mdelay(10);
+	}
+	outl(0, dev->base_addr + IMR_REG_OFFSET); 					// maybe we need to disable the all interrupt
+	priv->maccr = RX_BROADPKT | FULLDUP | CRC_APD | RX_FTL; 	// removed ENRX_IN_HALFTX. RX_FTL added for 802.1Q support
+
+	dbg_printk("MOXART Ethernet: finished moxart_mac_reset dev->base_addr=%x\n", (unsigned int) dev->base_addr);
+}
+
+static void moxart_mac_enable(struct net_device *dev)
+{
+	moxart_mac_priv_t *priv = netdev_priv(dev);
+	outl(0x00001010, dev->base_addr + ITC_REG_OFFSET);
+	outl(0x00000001, dev->base_addr + APTC_REG_OFFSET);
+	outl(0x00000390, dev->base_addr + DBLAC_REG_OFFSET);
+//	outl(RPKT_FINISH_M | NORXBUF_M | AHB_ERR_M, dev->base_addr + IMR_REG_OFFSET); // use NORXBUF_M to test interrupt
+	outl(RPKT_FINISH_M, dev->base_addr + IMR_REG_OFFSET);
+	priv->maccr |= (RCV_EN | XMT_EN | RDMA_EN | XDMA_EN);
+	outl(priv->maccr, dev->base_addr + MACCR_REG_OFFSET);
+
+	dbg_printk("MOXART Ethernet: finished moxart_mac_enable dev->base=%x\n", (unsigned int) dev->base_addr);
+}
+
+static void moxart_mac_setup_desc_ring(struct net_device *dev)
+{
+	moxart_mac_priv_t *priv = netdev_priv(dev);
+	tx_desc_t *txdesc;
+	rx_desc_t *rxdesc;
+	unsigned char *virtbuf;
+	unsigned int phybuf;
+	int i;
+
+	virtbuf = priv->virtTxBufBaseAddr;
+	phybuf = priv->phyTxBufBaseAddr;
+	for (i = 0; i < TX_DESC_NUM; i++, virtbuf += TX_BUF_SIZE, phybuf += TX_BUF_SIZE) {
+		txdesc = &priv->virtTxDescBaseAddr[i];
+		memset(txdesc, 0, sizeof(tx_desc_t));
+		txdesc->txdes2.phyTxBufBaseAddr = phybuf;
+		txdesc->txdes2.virtTxBufBaseAddr = virtbuf;
+	}
+	priv->virtTxDescBaseAddr[TX_DESC_NUM - 1].txdes1.ubit.Edotr = 1;
+
+	virtbuf = priv->virtRxBufBaseAddr;
+	phybuf = priv->phyRxBufBaseAddr;
+	for (i = 0; i < RX_DESC_NUM; i++, virtbuf += RX_BUF_SIZE, phybuf += RX_BUF_SIZE) {
+		rxdesc = &priv->virtRxDescBaseAddr[i];
+		memset(rxdesc, 0, sizeof(rx_desc_t));
+		rxdesc->rxdes0.ubit.RxDMAOwn = 1;
+		rxdesc->rxdes1.ubit.RxBufSize = RX_BUF_SIZE;
+		rxdesc->rxdes2.phyRxBufBaseAddr = phybuf;
+		rxdesc->rxdes2.virtRxBufBaseAddr = virtbuf;
+	}
+	priv->virtRxDescBaseAddr[RX_DESC_NUM - 1].rxdes1.ubit.Edorr = 1;
+	//dbg_printk("First Rx desc des0=0x%x, des1=%x\n", priv->virtRxDescBaseAddr[0].rxdes0.ui, priv->virtRxDescBaseAddr[0].rxdes1.ui);
+
+	priv->TxDescNow = priv->RxDescNow = 0;
+
+	// reset the MAC controler Tx/Rx desciptor base address
+	outl(priv->phyTxDescBaseAddr, dev->base_addr + TXR_BADR_REG_OFFSET);
+	outl(priv->phyRxDescBaseAddr, dev->base_addr + RXR_BADR_REG_OFFSET);
+
+	dbg_printk("MOXART Ethernet: finished moxart_mac_setup_desc_ring dev->base_addr=%x Tx/Rx desc phy=0x%x,0x%x, virt=0x%x,0x%x set Tx desc base address=0x%x, Rx=0x%x\n", (unsigned int) dev->base_addr, priv->phyTxDescBaseAddr, priv->phyRxDescBaseAddr, (unsigned int)priv->virtTxDescBaseAddr, (unsigned int)priv->virtRxDescBaseAddr, inl(dev->base_addr+TXR_BADR_REG_OFFSET), inl(dev->base_addr+RXR_BADR_REG_OFFSET));
+}
+
+static int moxart_mac_open(struct net_device *dev)
+{
+	moxart_mac_priv_t *priv = netdev_priv(dev);
+	if (!is_valid_ether_addr(dev->dev_addr)) {
+		return -EADDRNOTAVAIL;
+	}
+	spin_lock(&priv->txlock);
+	moxart_mac_reset(dev);
+	moxart_update_mac_address(dev);
+	moxart_mac_setup_desc_ring(dev);
+	moxart_mac_enable(dev);
+	spin_unlock(&priv->txlock);
+	netif_start_queue(dev);
+
+	dbg_printk("MOXART Ethernet: finished moxart_mac_open IMR=0x%x, MACCR=0x%x\n", inl(dev->base_addr+IMR_REG_OFFSET), inl(dev->base_addr+MACCR_REG_OFFSET));
+	return 0;
+}
+
+static int moxart_mac_stop(struct net_device *dev)
+{
+	moxart_mac_priv_t *priv = netdev_priv(dev);
+	netif_stop_queue(dev);
+	spin_lock(&priv->txlock);
+	outl(0, dev->base_addr + IMR_REG_OFFSET); 		// disable all interrupt
+	outl(0, dev->base_addr + MACCR_REG_OFFSET); 	// disable all function
+	spin_unlock(&priv->txlock);
+
+	dbg_printk("MOXART Ethernet: finished moxart_mac_stop\n");
+	return 0;
+}
+
+static void moxart_mac_recv(struct work_struct *ptr)
+{
+	struct net_device *dev = (struct net_device *) ptr;
+	moxart_mac_priv_t *priv = netdev_priv((struct net_device *)ptr);
+	rx_desc_t *rxdesc;
+	struct sk_buff *skb;
+	unsigned int ui, len;
+	int rxnow = priv->RxDescNow;
+	int loops=RX_DESC_NUM;
+
+	//dbg_printk("MOXART Ethernet: moxart_mac_recv\n");
+
+#if 0
+	dbg_printk("RxDescNow=%d, desc phy=0x%x, virt=0x%x, buf phy=0x%x, virt=0x%x\n", priv->RxDescNow, priv->phyRxDescBaseAddr+(priv->RxDescNow*sizeof(rx_desc_t)), (unsigned int)&priv->virtRxDescBaseAddr[priv->RxDescNow], priv->virtRxDescBaseAddr[priv->RxDescNow].rxdes2.phyRxBufBaseAddr, (unsigned int)priv->virtRxDescBaseAddr[priv->RxDescNow].rxdes2.virtRxBufBaseAddr);
+	dbg_printk("Now Rx desc des0=0x%x, des1=0x%x\n", priv->virtRxDescBaseAddr[priv->RxDescNow].rxdes0.ui, priv->virtRxDescBaseAddr[priv->RxDescNow].rxdes1.ui);
+#endif
+
+repeat_recv:
+	rxdesc = &priv->virtRxDescBaseAddr[rxnow];
+	ui = rxdesc->rxdes0.ui;
+
+	//if ( rxdesc->rxdes0.ubit.RxDMAOwn ) {
+	if (ui & RXDMA_OWN) {
+		return;
+	}
+
+	if (ui & (RX_ERR | CRC_ERR | FTL | RUNT | RX_ODD_NB)) {
+		dbg_printk("MOXART Ethernet: packet error !\n");
+		priv->stats.rx_dropped++;
+		priv->stats.rx_errors++;
+		goto recv_finish;
+	}
+
+	len = ui & RFL_MASK;
+	if (len > RX_BUF_SIZE) len = RX_BUF_SIZE;
+
+	skb = dev_alloc_skb(len + 2);
+	if (skb == NULL) {
+		dbg_printk("Allocate memory fail !\n");
+		priv->stats.rx_dropped++;
+		goto recv_finish;
+	}
+	skb_reserve(skb, 2);
+	skb->dev = dev;
+
+	memcpy(skb_put(skb, len), rxdesc->rxdes2.virtRxBufBaseAddr, len);
+	netif_rx(skb);
+
+	//dbg_printk("MOXART Ethernet: receive data pointer = 0x%x\n", (unsigned long)data);
+
+	skb->protocol = eth_type_trans(skb, dev);
+	dev->last_rx = jiffies;
+	priv->stats.rx_packets++;
+	priv->stats.rx_bytes += len;
+	if (ui & MULTICAST_RXDES0) priv->stats.multicast++;
+
+recv_finish:
+	rxdesc->rxdes0.ui = RXDMA_OWN;
+	rxnow++;
+	rxnow &= RX_DESC_NUM_MASK;
+	priv->RxDescNow = rxnow;
+	if ( loops-- > 0 ) {
+		goto repeat_recv;
+	}
+}
+
+static irqreturn_t moxart_mac_interrupt(int irq, void *dev_id /*, struct pt_regs *regs*/)
+{
+	struct net_device *dev = (struct net_device *) dev_id;
+	unsigned int ists = inl(dev->base_addr + ISR_REG_OFFSET);
+
+	//dbg_printk("MOXART Ethernet: moxart_mac_interrupt\n");
+
+	if (ists & RPKT_FINISH) {
+		moxart_mac_recv((void *) dev);
+	}
+	else {
+#ifdef moxart_MAC_DEBUG
+		if (ists & NORXBUF) {
+			dbg_printk("MOXART Ethernet: NORXBUF interrupt\n");
+			outl(inl(dev->base_addr + IMR_REG_OFFSET) & ~NORXBUF_M, dev->base_addr + IMR_REG_OFFSET);
+		}
+		if (ists & AHB_ERR) {
+			dbg_printk("MOXART Ethernet: AHB_ERR interrupt.\n");
+		}
+#endif
+	}
+	return IRQ_HANDLED;
+}
+
+static int moxart_mac_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	moxart_mac_priv_t *priv = netdev_priv(dev);
+	tx_desc_t *txdesc;
+	int len;
+	int txnow = priv->TxDescNow;
+
+	//dbg_printk("MOXART Ethernet: moxart_mac_hard_start_xmit\n");
+
+	spin_lock(&priv->txlock);
+	txdesc = &priv->virtTxDescBaseAddr[txnow];
+	if (txdesc->txdes0.ubit.TxDMAOwn) {
+		dbg_printk("MOXART Ethernet: no Tx space to transmit the packet !\n");
+		priv->stats.tx_dropped++;
+		goto xmit_final;
+	}
+
+	/*len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
+	len = len > TX_BUF_SIZE ? TX_BUF_SIZE : len;*/
+
+	len = skb->len > TX_BUF_SIZE ? TX_BUF_SIZE : skb->len;
+	memcpy(txdesc->txdes2.virtTxBufBaseAddr, skb->data, len);
+
+	if (skb->len < ETH_ZLEN) {
+		memset(&txdesc->txdes2.virtTxBufBaseAddr[skb->len], 0, ETH_ZLEN - skb->len);
+		len = ETH_ZLEN;
+	}
+
+	txdesc->txdes1.ubit.Lts = 1;
+	txdesc->txdes1.ubit.Fts = 1;
+	txdesc->txdes1.ubit.Tx2fic = 0;
+	txdesc->txdes1.ubit.Txic = 0;
+	txdesc->txdes1.ubit.TxBufSize = len;
+	txdesc->txdes0.ui = TXDMA_OWN;
+
+	dbg_printk("MOXART Ethernet: transmit data pointer = 0x%x\n", (unsigned int)skb->data);
+
+	outl(0xffffffff, dev->base_addr + TXPD_REG_OFFSET); // start to send packet
+
+#if 0
+			dbg_printk("TxDescNow=%d, address=0x%x, des0=0x%x, des1=0x%x\n", priv->TxDescNow, (unsigned int)&priv->virtTxDescBaseAddr[priv->TxDescNow], txdesc->txdes0.ui, txdesc->txdes1.ui);
+			dbg_printk("Buffer phy address=0x%x, virt=0x%x\n", txdesc->txdes2.phyTxBufBaseAddr, (unsigned int)txdesc->txdes2.virtTxBufBaseAddr);
+			dbg_printk("TxDescNow-1=%d, address=0x%x, des0=0x%x\n", (priv->TxDescNow-1)&TX_DESC_NUM_MASK, (unsigned int)&priv->virtTxDescBaseAddr[(priv->TxDescNow-1)&TX_DESC_NUM_MASK], priv->virtTxDescBaseAddr[(priv->TxDescNow-1)&TX_DESC_NUM_MASK].txdes0.ui);
+#endif
+
+	txnow++;
+	txnow &= TX_DESC_NUM_MASK;
+	priv->TxDescNow = txnow;
+	dev->trans_start = jiffies;
+	priv->stats.tx_packets++;
+	priv->stats.tx_bytes += len;
+
+xmit_final:
+	spin_unlock(&priv->txlock);
+	dev_kfree_skb_any(skb);
+
+	return NETDEV_TX_OK;
+}
+
+static struct net_device_stats *moxart_mac_get_stats(struct net_device *dev)
+{
+	moxart_mac_priv_t *priv = netdev_priv(dev);
+	unsigned int base=dev->base_addr;
+	int desc=priv->RxDescNow;
+
+	dbg_printk("MOXART Ethernet: moxart_mac_get_stats:\n");
+	dbg_printk("RxDescNow=%d, desc phy=0x%x, virt=0x%x, buf phy=0x%x, virt=0x%x Now Rx desc des0=0x%x, des1=0x%x\n", desc, priv->phyRxDescBaseAddr+(desc*sizeof(rx_desc_t)), (unsigned int)&priv->virtRxDescBaseAddr[desc], priv->virtRxDescBaseAddr[desc].rxdes2.phyRxBufBaseAddr, (unsigned int)priv->virtRxDescBaseAddr[desc].rxdes2.virtRxBufBaseAddr, priv->virtRxDescBaseAddr[desc].rxdes0.ui, priv->virtRxDescBaseAddr[desc].rxdes1.ui);
+	desc++;
+	desc &= RX_DESC_NUM_MASK;
+	dbg_printk("RxDescNow=%d, desc phy=0x%x, virt=0x%x, buf phy=0x%x, virt=0x%x Now Rx desc des0=0x%x, des1=0x%x (desc++)\n", desc, priv->phyRxDescBaseAddr+(desc*sizeof(rx_desc_t)), (unsigned int)&priv->virtRxDescBaseAddr[desc], priv->virtRxDescBaseAddr[desc].rxdes2.phyRxBufBaseAddr, (unsigned int)priv->virtRxDescBaseAddr[desc].rxdes2.virtRxBufBaseAddr, priv->virtRxDescBaseAddr[desc].rxdes0.ui, priv->virtRxDescBaseAddr[desc].rxdes1.ui);
+	dbg_printk("TX_MCOL_TX_SCOL=0x%x RPF_AEP=0x%x XM_PG=0x%x RUNT_CNT_TLCC=0x%x CRCER_CNT_FTL_CNT=0x%x RLC_RCC=0x%x BROC=0x%x MUCLA=0x%x RP=0x%x XP=0x%x\n", inl(base+TX_MCOL_TX_SCOL_REG_OFFSET), inl(base+RPF_AEP_REG_OFFSET), inl(base+XM_PG_REG_OFFSET), inl(base+RUNT_CNT_TLCC_REG_OFFSET), inl(base+CRCER_CNT_FTL_CNT_REG_OFFSET), inl(base+RLC_RCC_REG_OFFSET), inl(base+BROC_REG_OFFSET), inl(base+MULCA_REG_OFFSET), inl(base+RP_REG_OFFSET), inl(base+XP_REG_OFFSET));
+
+	return &priv->stats;
+}
+
+static struct net_device_ops moxart_netdev_ops = {
+	.ndo_open						= moxart_mac_open,
+	.ndo_stop						= moxart_mac_stop,
+	.ndo_start_xmit					= moxart_mac_start_xmit,
+	.ndo_get_stats					= moxart_mac_get_stats,
+#ifdef HAVE_MULTICAST
+//	.ndo_set_multicast_list			= moxart_mac_set_multicast_list,
+#endif
+	.ndo_set_mac_address			= moxart_set_mac_address,
+//	.ndo_do_ioctl					= moxart_mac_iotcl,
+	.ndo_validate_addr				= eth_validate_addr,
+	.ndo_change_mtu					= eth_change_mtu,
+//	.ndo_tx_timeout					= moxart_mac_tx_timeout,
+//	.ndo_init 						= moxart_mac_init,
+};
+
+/*static struct net_device moxart_mac1_dev = {
+	.name                            = "eth0",
+	.netdev_ops                      = &moxart_netdev_ops,
+};
+
+static struct net_device moxart_mac2_dev = {
+	.name                            = "eth1",
+	.netdev_ops                      = &moxart_netdev_ops,
+};*/
+
+static int __init moxart_mac_probe(struct platform_device *pdev)
+{
+	struct net_device *dev;
+	moxart_mac_priv_t *priv;
+	moxart_eth_data_t *pdata = (moxart_eth_data_t*)pdev->dev.platform_data;
+
+	dev = alloc_etherdev(sizeof(struct moxart_mac_priv_struct));
+	if (!dev) {
+		return -ENOMEM;
+	}
+
+	dev->base_addr = pdata->base_addr;
+	dev->irq = pdata->irq;
+
+	priv = netdev_priv(dev);
+	//memset((void *) priv, 0, sizeof(moxart_mac_priv_t));  // initialize the private variable to zero
+	spin_lock_init(&priv->txlock);
+	priv->virtTxDescBaseAddr = (tx_desc_t *) dma_alloc_coherent(NULL, sizeof(tx_desc_t) * TX_DESC_NUM, (dma_addr_t *)&priv->phyTxDescBaseAddr, GFP_DMA | GFP_KERNEL);
+	if ( priv->virtTxDescBaseAddr == NULL || (priv->phyTxDescBaseAddr & 0x0f) ) {
+		dbg_printk("Allocate the Tx descriptor memory fail !\n");
+		goto init_fail;
+	}
+	priv->virtRxDescBaseAddr = (rx_desc_t *) dma_alloc_coherent(NULL, sizeof(rx_desc_t) * RX_DESC_NUM, (dma_addr_t *)&priv->phyRxDescBaseAddr, GFP_DMA | GFP_KERNEL);
+	if ( priv->virtRxDescBaseAddr == NULL || (priv->phyRxDescBaseAddr & 0x0f) ) {
+		dbg_printk("Allocate the Rx descriptor memory fail !\n");
+		goto init_fail;
+	}
+	priv->virtTxBufBaseAddr = (unsigned char *) dma_alloc_coherent(NULL, TX_BUF_SIZE * TX_DESC_NUM, (dma_addr_t *)&priv->phyTxBufBaseAddr, GFP_DMA | GFP_KERNEL);
+	if ( priv->virtTxBufBaseAddr == NULL || (priv->phyTxBufBaseAddr & 0x03) ) {
+		dbg_printk("Allocate the Tx buffer memory fail !\n");
+		goto init_fail;
+	}
+	priv->virtRxBufBaseAddr = (unsigned char *) dma_alloc_coherent(NULL, RX_BUF_SIZE * RX_DESC_NUM, (dma_addr_t *)&priv->phyRxBufBaseAddr, GFP_DMA | GFP_KERNEL);
+	if ( priv->virtRxBufBaseAddr == NULL || (priv->phyRxBufBaseAddr & 0x03) ) {
+		dbg_printk("Allocate the Rx buffer memory fail !\n");
+		goto init_fail;
+	}
+	platform_set_drvdata(pdev, dev);
+
+	ether_setup(dev);
+	dev->netdev_ops = &moxart_netdev_ops;
+
+	SET_NETDEV_DEV(dev, &pdev->dev);
+
+	moxart_get_mac_address(dev, pdata->mac_addr_flash_offset);
+	moxart_update_mac_address(dev);
+
+	if (register_netdev(dev)) {
+		free_netdev(dev);
+		goto init_fail;
+	}
+
+	if (request_irq(dev->irq, &moxart_mac_interrupt, 0, dev->name, dev)) {
+		free_netdev(dev);
+		dbg_printk("MOXART Ethernet: request interrupt service failed\n");
+		return -EBUSY;
+	}
+
+	printk("MOXART Ethernet: finished moxart_mac_probe %s IRQ=%d address=%02x:%02x:%02x:%02x:%02x:%02x\n", dev->name, dev->irq, dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
+	return 0;
+
+init_fail:
+	printk("MOXART Ethernet: init_fail! \n");
+	moxart_mac_free_memory(dev);
+	return -ENOMEM;
+}
+
+static int __devexit moxart_remove(struct platform_device *pdev)
+{
+	struct net_device *dev = platform_get_drvdata(pdev);
+	unregister_netdev(dev);
+	free_irq(dev->irq, dev);
+	moxart_mac_free_memory(dev);
+	platform_set_drvdata(pdev, NULL);
+	free_netdev(dev);
+	return 0;
+}
+
+struct __initdata platform_driver moxart_mac_driver = {
+//	.probe       = &moxart_mac__probe,
+//	.suspend     = NULL,
+//	.resume      = NULL,
+	.remove      = __devexit_p(moxart_remove),
+	.driver      = {
+		.name	= "MOXART_RTL8201CP",
+		.owner	= THIS_MODULE,
+	},
+ };
+
+ static int __init moxart_mac_init(void)
+ {
+ 	 return platform_driver_probe(&moxart_mac_driver, moxart_mac_probe);
+ }
+
+static void __exit moxart_mac_exit(void)
+{
+	 platform_driver_unregister(&moxart_mac_driver);
+}
+
+module_init(moxart_mac_init)
+module_exit(moxart_mac_exit)
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MOXART RTL8201CP Ethernet driver");
+MODULE_AUTHOR("Jonas Jensen");
+MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/linux-2.6.32.60-mach-moxart/drivers/net/arm/moxart_ether.h b/linux-2.6.32.60-mach-moxart/drivers/net/arm/moxart_ether.h
new file mode 100644
index 0000000..02ebbcc
--- /dev/null
+++ b/linux-2.6.32.60-mach-moxart/drivers/net/arm/moxart_ether.h
@@ -0,0 +1,353 @@
+/* Copyright (C) 2012 Jonas Jensen <jonas.jensen@gmail.com> ( based on MOXA sources modified for 2.6.32.60 )
+ * This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. */
+
+#ifndef _MOXART_ETHERNET_H
+#define _MOXART_ETHERNET_H
+
+#define MOXART_ETHERNET_DEBUG
+
+#ifdef MOXART_ETHERNET_DEBUG
+#define dbg_printk(x...) printk(x)
+#else
+#define dbg_printk(x...)
+#endif
+
+#define TX_DESC_NUM         64
+#define TX_DESC_NUM_MASK    (TX_DESC_NUM-1)
+#define RX_DESC_NUM         64
+#define RX_DESC_NUM_MASK    (RX_DESC_NUM-1)
+#define TX_BUF_SIZE         1600
+#define RX_BUF_SIZE         1600
+
+typedef struct tx_desc_struct {
+	union {
+		unsigned int ui;
+#define TXDMA_OWN           (1<<31)
+#define TXPKT_EXSCOL        (1<<1)
+#define TXPKT_LATECOL       (1<<0)
+		struct {
+			unsigned int TxPktLateCol :1;  // is aborted due to late collision
+			unsigned int TxPktExsCol :1;   // is aborted after 16 collisions
+			unsigned int Reserved1 :29;
+			unsigned int TxDMAOwn :1;      // is owned by the MAC controller
+		} ubit;
+	} txdes0;
+	union {
+		unsigned int ui;
+#define EDOTR               (1<<31)
+#define TXIC                (1<<30)
+#define TX2FIC              (1<<29)
+#define FTS                 (1<<28)
+#define LTS                 (1<<27)
+#define TXBUF_SIZE_MASK     0x7ff
+#define TXBUF_SIZE_MAX      (TXBUF_SIZE_MASK+1)
+		struct {
+			unsigned int TxBufSize :11;    // transmit buffer size in byte
+			unsigned int Reserved2 :16;
+			unsigned int Lts :1;           // is the last descriptor of a Tx packet
+			unsigned int Fts :1;           // is the first descriptor of a Tx packet
+			unsigned int Tx2fic :1;        // transmit to FIFO interrupt on completion
+			unsigned int Txic :1;          // transmit interrupt on completion
+			unsigned int Edotr :1;         // end descriptor of transmit ring
+		} ubit;
+	} txdes1;
+	struct {
+		unsigned int phyTxBufBaseAddr;     // transmit buffer physical base address
+		unsigned char *virtTxBufBaseAddr;  // transmit buffer virtual base address
+	} txdes2;
+} tx_desc_t;
+
+typedef struct rx_desc_struct {
+	union {
+		unsigned int ui;
+#define RXDMA_OWN           (1<<31)
+#define FRS                 (1<<29)
+#define LRS                 (1<<28)
+#define RX_ODD_NB           (1<<22)
+#define RUNT                (1<<21)
+#define FTL                 (1<<20)
+#define CRC_ERR             (1<<19)
+#define RX_ERR              (1<<18)
+#define BROADCAST_RXDES0    (1<<17)
+#define MULTICAST_RXDES0    (1<<16)
+#define RFL_MASK        0x7ff
+#define RFL_MAX             (RFL_MASK+1)
+		struct {
+			unsigned int RecvFrameLen :11; // receive frame length
+			unsigned int Reserved1 :5;
+			unsigned int Multicast :1;     // multicast frame
+			unsigned int Broadcast :1;     // broadcast frame
+			unsigned int RxErr :1;         // receive error
+			unsigned int CRCErr :1;        // CRC error
+			unsigned int Ftl :1;           // frame too long
+			unsigned int Runt :1;          // runt packet, less than 64 bytes
+			unsigned int RxOddNb :1;       // receive odd nibbles
+			unsigned int Reserved2 :5;
+			unsigned int Lrs :1;           // last receive segment descriptor
+			unsigned int Frs :1;           // first receive segment descriptor
+			unsigned int Reserved3 :1;
+			unsigned int RxDMAOwn :1;      // RXDMA onwership
+		} ubit;
+	} rxdes0;
+	union {
+		unsigned int ui;
+#define EDORR               (1<<31)
+#define RXBUF_SIZE_MASK     0x7ff
+#define RXBUF_SIZE_MAX      (RXBUF_SIZE_MASK+1)
+		struct {
+			unsigned int RxBufSize :11;    // receive buffer size
+			unsigned int Reserved4 :20;
+			unsigned int Edorr :1;         // end descriptor of receive ring
+		} ubit;
+	} rxdes1;
+	struct {
+		unsigned int phyRxBufBaseAddr;     // receive buffer physical base address
+		unsigned char *virtRxBufBaseAddr;  // receive buffer virtual base address
+	} rxdes2;
+} rx_desc_t;
+
+typedef struct mac_control_reg_struct {
+	unsigned int isr;                      // interrupt status, 0x0
+#define RPKT_FINISH         (1<<0)         // RXDMA has received packets into RX buffer successfully
+#define NORXBUF             (1<<1)         // receive buffer unavailable
+#define XPKT_FINISH         (1<<2)         // TXDMA has moved data into the TX FIFO
+#define NOTXBUF             (1<<3)         // transmit buffer unavailable
+#define XPKT_OK_INT_STS     (1<<4)         // packets transmitted to ethernet successfully
+#define XPKT_LOST_INT_STS   (1<<5)         // packets transmitted to ethernet lost due to late collision or excessive collision
+#define RPKT_SAV            (1<<6)         // packets received into RX FIFO successfully
+#define RPKT_LOST_INT_STS   (1<<7)         // received packet lost due to RX FIFO full
+#define AHB_ERR             (1<<8)         // AHB error
+#define PHYSTS_CHG          (1<<9)         // PHY link status change
+	unsigned int imr;                      // interrupt mask, 0x4
+#define RPKT_FINISH_M       (1<<0)         // interrupt mask of ISR[0]
+#define NORXBUF_M           (1<<1)         // interrupt mask of ISR[1]
+#define XPKT_FINISH_M       (1<<2)         // interrupt mask of ISR[2]
+#define NOTXBUF_M           (1<<3)         // interrupt mask of ISR[3]
+#define XPKT_OK_M           (1<<4)         // interrupt mask of ISR[4]
+#define XPKT_LOST_M         (1<<5)         // interrupt mask of ISR[5]
+#define RPKT_SAV_M          (1<<6)         // interrupt mask of ISR[6]
+#define RPKT_LOST_M         (1<<7)         // interrupt mask of ISR[7]
+#define AHB_ERR_M           (1<<8)         // interrupt mask of ISR[8]
+#define PHYSTS_CHG_M        (1<<9)         // interrupt mask of ISR[9]
+	unsigned int mac_madr;                 // MAC most significant address, 0x8
+#define MAC_MADR_MASK       0xffff         // the most significant 2 bytes of MAC address
+	unsigned int mac_ldar;                 // MAC least significant address, 0xc
+	unsigned int matht0;                   // multicast address hash table 0, 0x10
+	unsigned int matht1;                   // multicast address hash table 1, 0x14
+	unsigned int txpd;                     // transmit poll demand, 0x18
+	unsigned int rxpd;                     // receive poll demand, 0x1c
+	unsigned int txr_badr;                 // transmit ring base address, 0x20
+	unsigned int rxr_badr;                 // receive ring base address, 0x24
+	unsigned int itc;                      // interrupt timer control, 0x28
+#define TXINT_TIME_SEL      (1<<15)        // defines the period of TX cycle time
+#define TXINT_THR_MASK      (1<<14|1<13|1<12)
+#define TXINT_CNT_MASK      (1<<11|1<<10|1<<9|1<<8)
+#define RXINT_TIME_SEL      (1<<7)         // defines the period of RX cycle time
+#define RXINT_THR_MASK      (1<<6|1<<5|1<<4)
+#define RXINT_CNT_MASK      (1<<3|1<<2|1<<1|1<<0)
+	unsigned int aptc;                     // automatic polling timer control, 0x2c
+#define TXPOLL_TIME_SEL     (1<<12)        // defines the period of TX poll time
+#define TXPOLL_CNT_MASK     (1<<11|1<<10|1<<9|1<<8)
+#define TXPOLL_CNT_SHIFT_BIT    8
+#define RXPOLL_TIME_SEL     (1<<4)         // defines the period of RX poll time
+#define RXPOLL_CNT_MASK     (1<<3|1<<2|1<<1|1<<0)
+#define RXPOLL_CNT_SHIFT_BIT    0
+	unsigned int dblac;                    // DMA burst length and arbitration control, 0x30
+#define RX_THR_EN           (1<<9)         // enable RX FIFO threshold arbitration
+#define RXFIFO_HTHR_MASK    (1<<8|1<<7|1<<6)
+#define RXFIFO_LTHR_MASK    (1<<5|1<<4|1<<3)
+#define INCR16_EN           (1<<2)         // use INCR16 burst command in AHB bus
+#define INCR8_EN            (1<<1)         // use INCR8 burst command in AHB bus
+#define INCR4_EN            (1<<0)         // use INCR4 burst command in AHB bus
+	unsigned int reserved1[21];            // 0x34 - 0x84
+	unsigned int maccr;                    // MAC control, 0x88
+#define RX_BROADPKT         (1<<17)        // receive boradcast packet
+#define RX_MULTIPKT         (1<<16)        // receive all multicast packet
+#define FULLDUP             (1<<15)        // full duplex
+#define CRC_APD             (1<<14)        // append CRC to transmitted packet
+#define RCV_ALL             (1<<12)        // not check incoming packet's dest. address
+#define RX_FTL              (1<<11)        // store incoming packet even if its length is great than 1518 bytes
+#define RX_RUNT             (1<<10)        // store incoming packet even if its length is less than 64 bytes
+#define HT_MULTI_EN         (1<<9)         // enable storing incoming packet if the packet passes hash table address filtering and is a multicast packet
+#define RCV_EN              (1<<8)         // receiver enable
+#define ENRX_IN_HALFTX      (1<<6)         // enable packet reception when transmitting packet in half duplex mode
+#define XMT_EN              (1<<5)         // transmitter enable
+#define CRC_DIS             (1<<4)         // disable CRC check when receiving packets
+#define LOOP_EN             (1<<3)         // internal loop-back
+#define SW_RST              (1<<2)         // software reset, last 64 AHB bus clocks
+#define RDMA_EN             (1<<1)         // enable receive DMA channel
+#define XDMA_EN             (1<<0)         // enable transmit DMA channel
+	unsigned int macsr;                    // MAC status, 0x8c
+#define COL_EXCEED          (1<<11)        // collision amount exceeds 16
+#define LATE_COL            (1<<10)        // transmitter detects late collision
+#define XPKT_LOST           (1<<9)         // packet transmitted to ethernet lost due to late collision or excessive collision
+#define XPKT_OK             (1<<8)         // packets transmitted to ethernet successfully
+#define RUNT_MAC_STS        (1<<7)         // receiver detects a runt packet
+#define FTL_MAC_STS         (1<<6)         // receiver detects a frame that is too long
+#define CRC_ERR_MAC_STS     (1<<5)
+#define RPKT_LOST           (1<<4)         // received packets list due to RX FIFO full
+#define RPKT_SAVE           (1<<3)         // packets received into RX FIFO successfully
+#define COL                 (1<<2)         // incoming packet dropped due to collision
+#define MCPU_BROADCAST      (1<<1)
+#define MCPU_MULTICAST      (1<<0)
+	unsigned int phycr;                    // PHY control, 0x90
+#define MIIWR               (1<<27)        // initialize a write sequence to PHY by setting this bit to 1. This bit would be auto cleared after the write operation is finished.
+#define MIIRD               (1<<26)
+#define REGAD_MASK          (1<<25|1<<24|1<<23|1<<22|1<<21)
+#define PHYAD_MASK          (1<<20|1<<19|1<<18|1<<17|1<<16)
+#define MIIRDATA_MASK       0xffff
+	unsigned int phywdata;                 // PHY write data, 0x94
+#define MIIWDATA_MASK       0xffff
+	unsigned int fcr;                      // flow control, 0x98
+#define PAUSE_TIME_MASK     0xffff0000
+#define FC_HIGH_MASK        (1<<15|1<<14|1<<13|1<<12)
+#define FC_LOW_MASK         (1<<11|1<<10|1<<9|1<<8)
+#define RX_PAUSE            (1<<4)         // receive pause frame
+#define TXPAUSED            (1<<3)         // packet transmission is paused due to receive
+										   // pause frame
+#define FCTHR_EN            (1<<2)         // enable flow control threshold mode.
+#define TX_PAUSE            (1<<1)         // transmit pause frame
+#define FC_EN               (1<<0)         // flow control mode enable
+	unsigned int bpr;                      // back pressure, 0x9c
+#define BK_LOW_MASK         (1<<11|1<<10|1<<9|1<<8)
+#define BKJAM_LEN_MASK      (1<<7|1<<6|1<<5|1<<4)
+#define BK_MODE             (1<<1)         // back pressure address mode
+#define BK_EN               (1<<0)         // back pressure mode enable
+	unsigned int reserved2[9];             // 0xa0 - 0xc0
+	unsigned int ts;                       // test seed, 0xc4
+#define TEST_SEED_MASK      0x3fff
+	unsigned int dmafifos;                 // DMA/FIFO state, 0xc8
+#define TXD_REQ             (1<<31)        // TXDMA request
+#define RXD_REQ             (1<<30)        // RXDMA request
+#define DARB_TXGNT          (1<<29)        // TXDMA grant
+#define DARB_RXGNT          (1<<28)        // RXDMA grant
+#define TXFIFO_EMPTY        (1<<27)        // TX FIFO is empty
+#define RXFIFO_EMPTY        (1<<26)        // RX FIFO is empty
+#define TXDMA2_SM_MASK      (1<<14|1<<13|1<<12)
+#define TXDMA1_SM_MASK      (1<<11|1<<10|1<<9|1<<8)
+#define RXDMA2_SM_MASK      (1<<6|1<<5|1<<4)
+#define RXDMA1_SM_MASK      (1<<3|1<<2|1<<1|1<<0)
+	unsigned int tm;                       // test mode, 0xcc
+#define SINGLE_PKT          (1<<26)        // single packet mode
+#define PTIMER_TEST         (1<<25)        // automatic polling timer test mode
+#define ITIMER_TEST         (1<<24)        // interrupt timer test mode
+#define TEST_SEED_SEL       (1<<22)        // test seed select
+#define SEED_SEL            (1<<21)        // seed select
+#define TEST_MODE           (1<<20)        // transmission test mode
+#define TEST_TIME_MASK      (1<<19|1<<18|1<<17|1<<16|1<<15|1<<14|1<<13|1<<12|1<<11|1<<10)
+#define TEST_EXCEL_MASK     (1<<9|1<<8|1<<7|1<<6|1<<5)
+	unsigned int reserved3;                // 0xd0
+	unsigned int txmcol_xscol;             // TX_MCOL and TX_SCOL counter, 0xd4
+#define TX_MCOL_MASK        0xffff0000
+#define TX_MCOL_SHIFT_BIT   16
+#define TX_SCOL_MASK        0xffff
+#define TX_SCOL_SHIFT_BIT   0
+	unsigned int rpf_aep;                  // RPF and AEP counter, 0xd8
+#define RPF_MASK        0xffff0000
+#define RPF_SHIFT_BIT       16
+#define AEP_MASK        0xffff
+#define AEP_SHIFT_BIT       0
+	unsigned int xm_pg;                    // XM and PG counter, 0xdc
+#define XM_MASK         0xffff0000
+#define XM_SHIFT_BIT        16
+#define PG_MASK         0xffff
+#define PG_SHIFT_BIT        0
+	unsigned int runtcnt_tlcc;             // RUNT_CNT and TLCC counter, 0xe0
+#define RUNT_CNT_MASK       0xffff0000
+#define RUNT_CNT_SHIFT_BIT  16
+#define TLCC_MASK       0xffff
+#define TLCC_SHIFT_BIT      0
+	unsigned int crcercnt_ftlcnt;          // CRCER_CNT and FTL_CNT counter, 0xe4
+#define CRCER_CNT_MASK      0xffff0000
+#define CRCER_CNT_SHIFT_BIT 16
+#define FTL_CNT_MASK        0xffff
+#define FTL_CNT_SHIFT_BIT   0
+	unsigned int rlc_rcc;                  // RLC and RCC counter, 0xe8
+#define RLC_MASK        0xffff0000
+#define RLC_SHIFT_BIT       16
+#define RCC_MASK        0xffff
+#define RCC_SHIFT_BIT       0
+	unsigned int broc;                     // BROC counter, 0xec
+	unsigned int mulca;                    // MULCA counter, 0xf0
+	unsigned int rp;                       // RP counter, 0xf4
+	unsigned int xp;                       // XP counter, 0xf8
+} mac_control_reg_t;
+
+#define ISR_REG_OFFSET                  0x00
+#define IMR_REG_OFFSET                  0x04
+#define MAC_MADR_REG_OFFSET             0x08
+#define MAC_LADR_REG_OFFSET             0x0C
+#define MATH0_REG_OFFSET                0x10
+#define MATH1_REG_OFFSET                0x14
+#define TXPD_REG_OFFSET                 0x18
+#define RXPD_REG_OFFSET                 0x1C
+#define TXR_BADR_REG_OFFSET             0x20
+#define RXR_BADR_REG_OFFSET             0x24
+#define ITC_REG_OFFSET                  0x28
+#define APTC_REG_OFFSET                 0x2C
+#define DBLAC_REG_OFFSET                0x30
+#define MACCR_REG_OFFSET                0x88
+#define MACSR_REG_OFFSET                0x8C
+#define PHYCR_REG_OFFSET                0x90
+#define PHYWDATA_REG_OFFSET             0x94
+#define FCR_REG_OFFSET                  0x98
+#define BPR_REG_OFFSET                  0x9C
+#define TS_REG_OFFSET                   0xC4
+#define DMAFIFOS_REG_OFFSET             0xC8
+#define TM_REG_OFFSET                   0xCC
+#define TX_MCOL_TX_SCOL_REG_OFFSET      0xD4
+#define RPF_AEP_REG_OFFSET              0xD8
+#define XM_PG_REG_OFFSET                0xDC
+#define RUNT_CNT_TLCC_REG_OFFSET        0xE0
+#define CRCER_CNT_FTL_CNT_REG_OFFSET    0xE4
+#define RLC_RCC_REG_OFFSET              0xE8
+#define BROC_REG_OFFSET                 0xEC
+#define MULCA_REG_OFFSET                0xF0
+#define RP_REG_OFFSET                   0xF4
+#define XP_REG_OFFSET                   0xF8
+
+/* Jimmy_chen@moxa.com.tw : phy ctrl register */
+#define PHY_CNTL_REG                               0x00
+#define PHY_STATUS_REG                             0x01
+#define PHY_ID_REG1                                0x02
+#define PHY_ID_REG2                                0x03
+#define PHY_ANA_REG                                0x04
+#define PHY_ANLPAR_REG                             0x05
+#define PHY_ANE_REG                                0x06
+#define PHY_ECNTL_REG1                             0x10
+#define PHY_QPDS_REG                               0x11
+#define PHY_10BOP_REG                              0x12
+#define PHY_ECNTL_REG2                             0x13
+#define FTMAC100_REG_PHY_WRITE                     0x08000000
+#define FTMAC100_REG_PHY_READ                      0x04000000
+/* PHY Status register */
+#define AN_COMPLETE 0x0020
+#define Link_Status 0x0004
+
+typedef struct moxart_mac_priv_struct {
+	unsigned int phyTxDescBaseAddr;        // Tx descriptor physical base address
+	tx_desc_t *virtTxDescBaseAddr;         // Tx descriptor virtual base address
+	unsigned int phyRxDescBaseAddr;        // Rx descriptor physical base address
+	rx_desc_t *virtRxDescBaseAddr;         // Rx descriptor virtual base address
+	unsigned int phyTxBufBaseAddr;         // Tx buffer physical base address
+	unsigned char *virtTxBufBaseAddr;      // Tx buffer virtual base address
+	unsigned int phyRxBufBaseAddr;         // Rx buffer physical base address
+	unsigned char *virtRxBufBaseAddr;      // Rx buffer virtual base address
+	int TxDescNow;                         // Tx descriptor now first used index
+	int RxDescNow;                         // Rx descriptor now first used index
+	struct net_device_stats stats;         // OS about the ethernet statistics
+	spinlock_t txlock;
+	spinlock_t rxlock;
+	unsigned int maccr;                    // store the maccr control register value
+	struct work_struct rqueue;
+} moxart_mac_priv_t;
+
+#if TX_BUF_SIZE >= TXBUF_SIZE_MAX
+#error Moxa CPU ethernet device driver Tx buffer size too large !
+#endif
+#if RX_BUF_SIZE >= RXBUF_SIZE_MAX
+#error Moxa CPU ethernet device driver Rx buffer size too large !
+#endif
+
+#endif                                     // MOXACPU_MAC_H
