diff -Naur simulavr-0.1.2.7/src/defn/mega8.h simulavr-20110806/src/defn/mega8.h
--- simulavr-0.1.2.7/src/defn/mega8.h	2009-03-02 06:51:18.000000000 +0000
+++ simulavr-20110806/src/defn/mega8.h	2011-08-01 16:38:21.000000000 +0000
@@ -26,6 +26,10 @@
 #if defined (IN_DEVSUPP_C)
 /* *INDENT-OFF* */
 
+static uint8_t timer1_def_8 = TD_TIMER1;
+static uint8_t timer_mask_8 = (mask_TICIE1_m8 | mask_OCIE1A_m8 
+                             | mask_OCIE1B_m8 | mask_TOIE1_m8);
+
 static DevSuppDefn defn_atmega8 = {
     .name           = "atmega8",
     .stack_type     = STACK_MEMORY,
@@ -168,10 +172,38 @@
         { .addr = 0x49, .name = "OCR1BH", },
         { .addr = 0x4a, .name = "OCR1AL", },
         { .addr = 0x4b, .name = "OCR1AH", },
-        { .addr = 0x4c, .name = "TCNT1L", },
-        { .addr = 0x4d, .name = "TCNT1H", },
-        { .addr = 0x4e, .name = "TCCR1B", },
-        { .addr = 0x4f, .name = "TCCR1A", },
+        {	.addr = 0x4c,
+		.name = "TCNT1L", 		//TCNT1L
+		.related = 0x58,
+		.vdev_create=timer16_create,
+		.data=&timer1_def_8,
+		.reset_value = 0,
+	        .rd_mask = 0xff,
+          	.wr_mask = 0xff,
+	},
+        {	.addr = 0x4d,
+		.name = "TCNT1H",
+		.ref_addr = 0x4c,
+		.reset_value = 0,
+	        .rd_mask = 0xff,
+          	.wr_mask = 0xff,
+	 },
+        {
+            .addr = 0x4e,
+            .name = "TCCR1B",
+            .ref_addr = 0x4c,
+            .reset_value = 0,
+            .rd_mask = 0xff,
+            .wr_mask = 0xff,
+		},
+        {
+            .addr = 0x4f,
+            .name = "TCCR1A",
+            .ref_addr = 0x4c,
+            .reset_value = 0,
+            .rd_mask = 0xff,
+            .wr_mask = 0xff,
+        },
         { .addr = 0x50, .name = "SFIOR", },
         { .addr = 0x51, .name = "OSCCAL", },
         { .addr = 0x52, .name = "TCNT0", },
@@ -180,8 +212,23 @@
         { .addr = 0x55, .name = "MCUCR", },
         { .addr = 0x56, .name = "TWCR", },
         { .addr = 0x57, .name = "SPMCR", },
-        { .addr = 0x58, .name = "TIFR", },
-        { .addr = 0x59, .name = "TIMSK", },
+        {
+            .addr = 0x58,
+            .name = "TIFR",
+            .vdev_create = timer_int_create,
+            .data = &(timer_mask_8),
+            .reset_value = 0,
+            .rd_mask = 0xff,
+            .wr_mask = 0xff,
+	},
+        {
+            .addr = 0x59, 
+            .name = "TIMSK", 
+            .ref_addr = 0x58,
+            .reset_value = 0,
+	    .rd_mask = 0xff,
+            .wr_mask = 0xff,
+	},
         { .addr = 0x5a, .name = "GIFR", },
         { .addr = 0x5b, .name = "GICR", },
         {
diff -Naur simulavr-0.1.2.7/src/devsupp.c simulavr-20110806/src/devsupp.c
--- simulavr-0.1.2.7/src/devsupp.c	2008-03-19 22:39:01.000000000 +0000
+++ simulavr-20110806/src/devsupp.c	2011-08-06 08:06:51.000000000 +0000
@@ -74,6 +74,7 @@
  * The value is an index into the global_vtable_list[] array 
  * defined in intvects.c.
  */
+/* - move to devsupp.h
 enum _vector_table_select
 {
     VTAB_AT90S1200 = 0,
@@ -89,7 +90,7 @@
     VTAB_AT43USB325,
     VTAB_AT43USB326,
 };
-
+*/
 /* IO Register Definition.  */
 
 struct io_reg_defn {
diff -Naur simulavr-0.1.2.7/src/devsupp.h simulavr-20110806/src/devsupp.h
--- simulavr-0.1.2.7/src/devsupp.h	2008-03-19 22:39:02.000000000 +0000
+++ simulavr-20110806/src/devsupp.h	2011-07-30 16:26:54.000000000 +0000
@@ -23,6 +23,22 @@
  ****************************************************************************
  */
 
+enum _vector_table_select
+{
+    VTAB_AT90S1200 = 0,
+    VTAB_AT90S2313,
+    VTAB_AT90S4414,
+    VTAB_ATMEGA8,
+    VTAB_ATMEGA16,
+    VTAB_ATMEGA32,
+    VTAB_ATMEGA103,
+    VTAB_ATMEGA128,
+    VTAB_AT43USB355,
+    VTAB_AT43USB320,
+    VTAB_AT43USB325,
+    VTAB_AT43USB326,
+};
+
 #ifndef SIM_DEVSUPP_H
 #define SIM_DEVSUPP_H
 
diff -Naur simulavr-0.1.2.7/src/timers.c simulavr-20110806/src/timers.c
--- simulavr-0.1.2.7/src/timers.c	2004-03-13 19:55:34.000000000 +0000
+++ simulavr-20110806/src/timers.c	2011-08-06 08:27:35.000000000 +0000
@@ -59,6 +59,8 @@
 
 #include "intvects.h"
 
+#include "devsupp.h"
+
 #ifndef DOXYGEN
 
 /* *INDENT-OFF* */
@@ -297,30 +299,30 @@
          *   many interrupts pending and then the user wants to clear one.
          */
 
-        if (intrs & mask_TOV0)
+        if (intrs & core->irq_vtable[irq_vect_table_index(TIMER0_OVF)].flag.mask)
         {
             avr_core_irq_raise (core, irq_vect_table_index (TIMER0_OVF));
-            ti->tifr &= ~mask_TOV0;
+            ti->tifr &= ~ core->irq_vtable[irq_vect_table_index(TIMER0_OVF)].flag.mask;
         }
-        else if (intrs & mask_ICF1)
+        else if (intrs &  core->irq_vtable[irq_vect_table_index(TIMER1_CAPT)].flag.mask)
         {
             avr_core_irq_raise (core, irq_vect_table_index (TIMER1_CAPT));
-            ti->tifr &= ~mask_ICF1;
+            ti->tifr &= ~ core->irq_vtable[irq_vect_table_index(TIMER1_CAPT)].flag.mask;
         }
-        else if (intrs & mask_OCF1B)
+        else if (intrs &  core->irq_vtable[irq_vect_table_index(TIMER1_COMPB)].flag.mask)
         {
             avr_core_irq_raise (core, irq_vect_table_index (TIMER1_COMPB));
-            ti->tifr &= ~mask_OCF1B;
+            ti->tifr &= ~ core->irq_vtable[irq_vect_table_index(TIMER1_COMPB)].flag.mask;
         }
-        else if (intrs & mask_OCF1A)
+        else if (intrs &  core->irq_vtable[irq_vect_table_index(TIMER1_COMPA)].flag.mask)
         {
             avr_core_irq_raise (core, irq_vect_table_index (TIMER1_COMPA));
-            ti->tifr &= ~mask_OCF1A;
+            ti->tifr &= ~ core->irq_vtable[irq_vect_table_index(TIMER1_COMPA)].flag.mask;
         }
-        else if (intrs & mask_TOV1)
+        else if (intrs & core->irq_vtable[irq_vect_table_index(TIMER1_OVF)].flag.mask)
         {
             avr_core_irq_raise (core, irq_vect_table_index (TIMER1_OVF));
-            ti->tifr &= ~mask_TOV1;
+            ti->tifr &= ~core->irq_vtable[irq_vect_table_index(TIMER1_OVF)].flag.mask;
         }
         else
         {
@@ -532,6 +534,7 @@
                                                    vdev_get_core ((VDevice *)
                                                                   timer),
                                                    timer->related_addr);
+        AvrCore *core = (AvrCore *)vdev_get_core ((VDevice *)timer);
 
     if (timer->clk_cb == NULL)
         return CB_RET_REMOVE;
@@ -552,7 +555,7 @@
        interpretation of the datasheets. See datasheet discussion of TIFR.
        TRoth */
     if ((timer->tcnt == 0) && (timer->tcnt != last))
-        ti->tifr |= mask_TOV0;
+        ti->tifr |= core->irq_vtable[irq_vect_table_index(TIMER0_OVF)].flag.mask;
 
     return CB_RET_RETAIN;
 }
@@ -633,21 +636,41 @@
         ti->tcntl_addr = addr;
     }
 
+    else if (strncmp ("TCNT1L", name, 6) == 0)
+    {
+        ti->tcntl_addr = addr;
+    }
+
     else if (strncmp ("TCNTH", name, 5) == 0)
     {
         ti->tcnth_addr = addr;
     }
 
+    else if (strncmp ("TCNT1H", name, 6) == 0)
+    {
+        ti->tcnth_addr = addr;
+    }
+
     else if (strncmp ("TCCRA", name, 5) == 0)
     {
         ti->tccra_addr = addr;
     }
 
+    else if (strncmp ("TCCR1A", name, 6) == 0)
+    {
+        ti->tccra_addr = addr;
+    }
+
     else if (strncmp ("TCCRB", name, 5) == 0)
     {
         ti->tccrb_addr = addr;
     }
 
+    else if (strncmp ("TCCR1B", name, 6) == 0)
+    {
+        ti->tccrb_addr = addr;
+    }
+
     else if (strncmp ("TCCRC", name, 5) == 0)
     {
         ti->tccrc_addr = addr;
@@ -782,6 +805,7 @@
                                                                       *)
                                                                      timer),
                                                       timer->related_addr);
+	AvrCore *core=(AvrCore *)vdev_get_core ((VDevice *)timer);
 
     if (timer->clk_cb == NULL)
         return CB_RET_REMOVE;
@@ -800,17 +824,17 @@
     {
         /* An overflow occurred */
         if (timer->tcnt == 0)
-            timer_intr_set_flag (timer->ti, mask_TOV1);
+                   timer_intr_set_flag (timer->ti, core->irq_vtable[irq_vect_table_index(TIMER1_OVF)].flag.mask);
 
         /* The counter value matches one of the ocr values */
         if (timer->ocra && (timer->tcnt == timer->ocra->ocr))
         {
-            timer_intr_set_flag (timer->ti, mask_OCF1A);
+            timer_intr_set_flag (timer->ti, core->irq_vtable[irq_vect_table_index(TIMER1_COMPA)].flag.mask);
         }
 
         if (timer->ocrb && (timer->tcnt == timer->ocrb->ocr))
         {
-            timer_intr_set_flag (timer->ti, mask_OCF1B);
+            timer_intr_set_flag (timer->ti, core->irq_vtable[irq_vect_table_index(TIMER1_COMPB)].flag.mask);
         }
     }
     return CB_RET_RETAIN;
diff -Naur simulavr-0.1.2.7/src/timers.h simulavr-20110806/src/timers.h
--- simulavr-0.1.2.7/src/timers.h	2004-03-13 19:55:34.000000000 +0000
+++ simulavr-20110806/src/timers.h	2011-07-30 18:25:52.000000000 +0000
@@ -62,6 +62,33 @@
     mask_TOIE1 = 1 << bit_TOIE1,
 } TIMSK_MASKS;
 
+//atmega8
+typedef enum
+{
+    bit_TOIE0_m8 = 0,           /* timer/counter0 overflow interrupt enable */
+    bit_TOIE1_m8 = 2,           /* timer/counter1 overflow interrupt enable */
+    bit_OCIE1B_m8 = 3,          /* timer/counter1 output compare B match
+                                   enable */
+    bit_OCIE1A_m8 = 4,          /* timer/counter1 output compare A match
+                                   interrupt enable */
+    bit_TICIE1_m8 = 5,          /* timer/counter1 input capture interrupt
+                                   interrupt enable */
+    bit_TOIE2_m8 = 6,           /* timer/counter1 overflow interrupt enable */
+    bit_OCIE2_m8 = 7,           /* timer/counter1 output compare match 
+                                   interrupt enable */
+} TIMSK_BITS_m8;
+
+typedef enum
+{
+    mask_TOIE0_m8 = 1 << bit_TOIE0_m8,
+    mask_TOIE1_m8 = 1 << bit_TOIE1_m8,
+    mask_OCIE1B_m8 = 1 << bit_OCIE1B_m8,
+    mask_OCIE1A_m8 = 1 << bit_OCIE1A_m8,
+    mask_TICIE1_m8 = 1 << bit_TICIE1_m8,
+    mask_TOIE2_m8 = 1 << bit_TOIE2_m8,
+    mask_OCIE2_m8 = 1 << bit_OCIE2_m8,
+} TIMSK_MASKS_m8;
+
 typedef enum
 {
     bit_TOV0 = 1,               /* timer/counter0 overflow flag */
@@ -73,12 +100,25 @@
 
 typedef enum
 {
-    mask_TOV0 = 1 << bit_TOV0,
-    mask_ICF1 = 1 << bit_ICF1,
-    mask_OCF1B = 1 << bit_OCF1B,
-    mask_OCF1A = 1 << bit_OCF1A,
-    mask_TOV1 = 1 << bit_TOV1,
-} TIFR_MASKS;
+    bit_TOV0_m8 = 0,            /* timer/counter0 overflow flag */
+    bit_TOV1_m8 = 2,            /* timer/counter1 overflow flag */
+    bit_OCF1B_m8 = 3,           /* output compare flag 1B */
+    bit_OCF1A_m8 = 4,           /* output compare flag 1A */
+    bit_ICF1_m8 = 5,            /* input capture flag 1 */
+    bit_TOV2_m8 = 6,            /* timer/counter2 overflow flag */
+    bit_OCF2_m8 = 7             /* output compare flag 2 */
+} TIFR_BITS_m8;
+
+typedef enum
+{
+    mask_TOV0_m8 = 1 << bit_TOV0_m8,
+    mask_TOV1_m8 = 1 << bit_TOV1_m8,
+    mask_OCF1B_m8 = 1 << bit_OCF1B_m8,
+    mask_OCF1A_m8 = 1 << bit_OCF1A_m8,
+    mask_ICF1_m8 = 1 << bit_ICF1_m8,
+    mask_TOV2_m8 = 1 << bit_TOV2_m8,
+    mask_OCF2_m8 = 1 << bit_OCF2_m8,
+} TIFR_MASKS_m8;
 
 typedef struct _TimerIntr_T TimerIntr_T;
 
