Index: power.h
===================================================================
--- power.h	(révision 2179)
+++ power.h	(copie de travail)
@@ -1,4 +1,5 @@
 /* Copyright (c) 2006, 2007, 2008  Eric B. Weddington
+   Copyright (c) 2010 Frédéric Nadeau
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -1375,11 +1376,22 @@
 when the need for processing power is low. Below are two macros and an
 enumerated type that can be used to interface to the Clock Prescale Register.
 
-\note Not all AVR devices have a Clock Prescale Register. On those devices
-without a Clock Prescale Register, these macros are not available.
+Some devices have the XTAL Divide Control Register which offer similar
+functionnality than System Clock Prescale Register. Both macro are available
+for these devices.
+
+\note Not all AVR devices have a Clock Prescale Register or XTAL Divide Control
+Register. On those devices without a Clock Prescale Register or XTAL Divide
+Control Register, these macros are not available.
+
+\note For device using the XTAL Divide Control Register (XDIV), when prescaller
+is used, Timer/Counter0 can only be used in asynchronous mode. Keep in mind
+that Timer/Counter0 source shall be less than ¼th of peripheral clock.
+Therefore, when using a typical 32.768 kHz, one shall not scale the clock
+below 131.072 khz.
+
 */
 
-
 /** \addtogroup avr_power
 \code 
 typedef enum
@@ -1396,8 +1408,25 @@
     clock_div_1_rc = 15, // ATmega128RFA1 only
 } clock_div_t;
 \endcode
-Clock prescaler setting enumerations.
+Clock prescaler setting enumerations for device with System Clock Prescale
+Register (CLKPR).
 
+\code
+typedef enum
+{
+    clock_div_1 = 1,
+    clock_div_2 = 2,
+    clock_div_4 = 4,
+    clock_div_8 = 8,
+    clock_div_16 = 16,
+    clock_div_32 = 32,
+    clock_div_64 = 64,
+    clock_div_128 = 128
+} clock_div_t;
+\endcode
+Clock prescaler setting enumerations for device with XTAL Divide Control
+Register (XDIV).
+
 */
 typedef enum
 {
@@ -1426,6 +1455,9 @@
 optimizations are disabled.
 
 The type of x is clock_div_t.
+
+\note For device with XTAL Divide Control Register (XDIV), x can actually range
+from 1 to 127.
 */
 void clock_prescale_set(clock_div_t __x)
 {
@@ -1506,10 +1538,69 @@
 
 #define clock_prescale_get()  (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
 
+#elif defined(__AVR_ATmega128__) \
+|| defined(__AVR_ATmega128A__) \
+|| defined(__AVR_ATmega64__) \
+|| defined(__AVR_ATmega64A__)
 
-#endif
+//May be removed if function are rewriten in assembly
+#include <util/atomic.h>
 
+//Enum is declared for code compatibility
+typedef enum
+{
+    clock_div_1 = 1,
+    clock_div_2 = 2,
+    clock_div_4 = 4,
+    clock_div_8 = 8,
+    clock_div_16 = 16,
+    clock_div_32 = 32,
+    clock_div_64 = 64,
+    clock_div_128 = 128
+} clock_div_t;
 
+void clock_prescale_set(clock_div_t x)
+{
+    if(x <= 0)
+    {
+        return;//Invalid value.
+    }
 
+    //See Atmel erreta
+    //Stabilizing time needed when changing XDIV Register
+    ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
+    {
+        if(x == 1)//Disable prescaler
+        {
+            XDIV = 0;
+        }
+        else if(x <= 127)
+        {
+            XDIV = (129 - x) | _BV(XDIVEN);
+        }
+        asm("NOP");
+        asm("NOP");
+        asm("NOP");
+        asm("NOP");
+        asm("NOP");
+        asm("NOP");
+        asm("NOP");
+        asm("NOP");
+    }
+}
 
+clock_div_t clock_prescale_get(void)
+{
+    if(bit_is_clear(XDIV, XDIVEN))
+    {
+        return 1;
+    }
+    else
+    {
+        return (clock_div_t)(129 - (XDIV & 0x7F));
+    }
+}
+
+#endif
+
 #endif /* _AVR_POWER_H_ */
Index: power.h
===================================================================
--- power.h	(révision 2179)
+++ power.h	(copie de travail)
@@ -1,4 +1,5 @@
 /* Copyright (c) 2006, 2007, 2008  Eric B. Weddington
+   Copyright (c) 2010 Frédéric Nadeau
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -1375,11 +1376,22 @@
 when the need for processing power is low. Below are two macros and an
 enumerated type that can be used to interface to the Clock Prescale Register.
 
-\note Not all AVR devices have a Clock Prescale Register. On those devices
-without a Clock Prescale Register, these macros are not available.
+Some devices have the XTAL Divide Control Register which offer similar
+functionnality than System Clock Prescale Register. Both macro are available
+for these devices.
+
+\note Not all AVR devices have a Clock Prescale Register or XTAL Divide Control
+Register. On those devices without a Clock Prescale Register or XTAL Divide
+Control Register, these macros are not available.
+
+\note For device using the XTAL Divide Control Register (XDIV), when prescaller
+is used, Timer/Counter0 can only be used in asynchronous mode. Keep in mind
+that Timer/Counter0 source shall be less than ¼th of peripheral clock.
+Therefore, when using a typical 32.768 kHz, one shall not scale the clock
+below 131.072 khz.
+
 */
 
-
 /** \addtogroup avr_power
 \code 
 typedef enum
@@ -1396,8 +1408,25 @@
     clock_div_1_rc = 15, // ATmega128RFA1 only
 } clock_div_t;
 \endcode
-Clock prescaler setting enumerations.
+Clock prescaler setting enumerations for device with System Clock Prescale
+Register (CLKPR).
 
+\code
+typedef enum
+{
+    clock_div_1 = 1,
+    clock_div_2 = 2,
+    clock_div_4 = 4,
+    clock_div_8 = 8,
+    clock_div_16 = 16,
+    clock_div_32 = 32,
+    clock_div_64 = 64,
+    clock_div_128 = 128
+} clock_div_t;
+\endcode
+Clock prescaler setting enumerations for device with XTAL Divide Control
+Register (XDIV).
+
 */
 typedef enum
 {
@@ -1426,6 +1455,9 @@
 optimizations are disabled.
 
 The type of x is clock_div_t.
+
+\note For device with XTAL Divide Control Register (XDIV), x can actually range
+from 1 to 127.
 */
 void clock_prescale_set(clock_div_t __x)
 {
@@ -1506,10 +1538,68 @@
 
 #define clock_prescale_get()  (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
 
+#elif defined(__AVR_ATmega128__) \
+|| defined(__AVR_ATmega128A__) \
+|| defined(__AVR_ATmega64__) \
+|| defined(__AVR_ATmega64A__)
 
-#endif
+#include <util/atomic.h>
 
+//Enum is declared for code compatibility
+typedef enum
+{
+    clock_div_1 = 1,
+    clock_div_2 = 2,
+    clock_div_4 = 4,
+    clock_div_8 = 8,
+    clock_div_16 = 16,
+    clock_div_32 = 32,
+    clock_div_64 = 64,
+    clock_div_128 = 128
+} clock_div_t;
 
+void clock_prescale_set(clock_div_t x)
+{
+    if(x <= 0)
+    {
+        return;//Invalid value.
+    }
 
+    //See Atmel erreta
+    //Stabilizing time needed when changing XDIV Register
+    ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
+    {
+        if(x == 1)//Disable prescaler
+        {
+            XDIV = 0;
+        }
+        else if(x <= 127)
+        {
+            XDIV = (129 - x) | _BV(XDIVEN);
+        }
+        asm("NOP");
+        asm("NOP");
+        asm("NOP");
+        asm("NOP");
+        asm("NOP");
+        asm("NOP");
+        asm("NOP");
+        asm("NOP");
+    }
+}
 
+clock_div_t clock_prescale_get(void)
+{
+    if(bit_is_clear(XDIV, XDIVEN))
+    {
+        return 1;
+    }
+    else
+    {
+        return (clock_div_t)(129 - (XDIV & 0x7F));
+    }
+}
+
+#endif
+
 #endif /* _AVR_POWER_H_ */
Index: power.h
===================================================================
--- power.h	(révision 2179)
+++ power.h	(copie de travail)
@@ -1,4 +1,5 @@
 /* Copyright (c) 2006, 2007, 2008  Eric B. Weddington
+   Copyright (c) 2010 Frédéric Nadeau
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -1372,14 +1373,27 @@
 
 Some of the newer AVRs contain a System Clock Prescale Register (CLKPR) that
 allows you to decrease the system clock frequency and the power consumption
-when the need for processing power is low. Below are two macros and an
-enumerated type that can be used to interface to the Clock Prescale Register.
+when the need for processing power is low.
 
-\note Not all AVR devices have a Clock Prescale Register. On those devices
-without a Clock Prescale Register, these macros are not available.
+Some devices have the XTAL Divide Control Register which offer similar
+functionnality than System Clock Prescale Register.
+
+Below are two macros and an enumerated type that can be used to interface to
+either the Clock Prescale Register or the XTAL Divide Control Register
+depending on your device capability.
+
+\note Not all AVR devices have a Clock Prescale Register or XTAL Divide Control
+Register. On those devices without a Clock Prescale Register or XTAL Divide
+Control Register, these macros are not available.
+
+\note For device using the XTAL Divide Control Register (XDIV), when prescaller
+is used, Timer/Counter0 can only be used in asynchronous mode. Keep in mind
+that Timer/Counter0 source shall be less than ¼th of peripheral clock.
+Therefore, when using a typical 32.768 kHz, one shall not scale the clock
+below 131.072 khz.
+
 */
 
-
 /** \addtogroup avr_power
 \code 
 typedef enum
@@ -1396,8 +1410,24 @@
     clock_div_1_rc = 15, // ATmega128RFA1 only
 } clock_div_t;
 \endcode
-Clock prescaler setting enumerations.
+Clock prescaler setting enumerations for device with System Clock Prescale
+Register (CLKPR).
 
+\code
+typedef enum
+{
+    clock_div_1 = 1,
+    clock_div_2 = 2,
+    clock_div_4 = 4,
+    clock_div_8 = 8,
+    clock_div_16 = 16,
+    clock_div_32 = 32,
+    clock_div_64 = 64
+} clock_div_t;
+\endcode
+Clock prescaler setting enumerations for device with XTAL Divide Control
+Register (XDIV).
+
 */
 typedef enum
 {
@@ -1426,6 +1456,11 @@
 optimizations are disabled.
 
 The type of x is clock_div_t.
+
+\note For device with XTAL Divide Control Register (XDIV), x can actually range
+from 1 to 128. Thus, one does not need to use clock_div_t type as argument.
+Remember that gcc will interprete enums as generic type, most likely as
+unsigned char here.
 */
 void clock_prescale_set(clock_div_t __x)
 {
@@ -1447,6 +1482,11 @@
 \code clock_prescale_get() \endcode
 Gets and returns the clock prescaler register setting. The return type is clock_div_t.
 
+\note For device with XTAL Divide Control Register (XDIV), return can actually
+range from 1 to 128. Thus, one does not need to use clock_div_t type as
+argument. Remember that gcc will interprete enums as generic type, most likely
+as unsigned char here.
+
 */
 #define clock_prescale_get()  (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
 
@@ -1506,10 +1546,91 @@
 
 #define clock_prescale_get()  (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
 
+#elif defined(__AVR_ATmega103__) \
+|| defined(__AVR_ATmega128__) \
+|| defined(__AVR_ATmega64__)
 
-#endif
+#include <util/atomic.h>
 
+//Enum is declared for code compatibility
+typedef enum
+{
+    clock_div_1 = 1,
+    clock_div_2 = 2,
+    clock_div_4 = 4,
+    clock_div_8 = 8,
+    clock_div_16 = 16,
+    clock_div_32 = 32,
+    clock_div_64 = 64,
+    clock_div_128 = 128
+} clock_div_t;
 
+void clock_prescale_set(clock_div_t __x)
+{
+    if((__x <= 0) || (__x > 129))
+    {
+        return;//Invalid value.
+    }
+    else
+        {
+        uint8_t __tmp = 0;
+        //Algo explain:
+        //1 - Clear XDIV in order for it to accept a new value (actually only
+        //    XDIVEN need to be cleared, but clearing XDIV is faster than
+        //    read-modify-write since we will rewrite XDIV later anyway).
+        //2 - wait 8 clock cycle for stability
+        //3 - Exist if requested prescaller is 1
+        //4 - Calculate XDIV6..0 value = 129 - __x
+        //5 - Set XDIVEN bit
+        //6 - write XDIV with calculated value
+        //7 - wait 8 clock cycle for stability
+        __asm__ __volatile__ (
+            "in __tmp_reg__,__SREG__" "\n\t"
+            "cli" "\n\t"
+            "out %1, __zero_reg__" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "cpi %0, 0x01" "\n\t"
+            "breq L_%=" "\n\t"
+            "ldi %2, 0x81" "\n\t" //129
+            "sub %2, %0" "\n\t"
+            "ori %2, 0x80" "\n\t" //128
+            "out %1, %2" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "L_%=: " "out __SREG__, __tmp_reg__"
+            : /* no outputs */
+            :"d" (__x),
+             "I" (_SFR_IO_ADDR(XDIV)),
+             "d" (__tmp)
+            : "r0");
+        }
+}
 
+clock_div_t clock_prescale_get(void)
+{
+    if(bit_is_clear(XDIV, XDIVEN))
+    {
+        return 1;
+    }
+    else
+    {
+        return (clock_div_t)(129 - (XDIV & 0x7F));
+    }
+}
 
+#endif
+
 #endif /* _AVR_POWER_H_ */
Index: power.h
===================================================================
--- power.h	(révision 2179)
+++ power.h	(copie de travail)
@@ -1,4 +1,5 @@
 /* Copyright (c) 2006, 2007, 2008  Eric B. Weddington
+   Copyright (c) 2010 Frédéric Nadeau
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -1372,14 +1373,27 @@
 
 Some of the newer AVRs contain a System Clock Prescale Register (CLKPR) that
 allows you to decrease the system clock frequency and the power consumption
-when the need for processing power is low. Below are two macros and an
-enumerated type that can be used to interface to the Clock Prescale Register.
+when the need for processing power is low.
 
-\note Not all AVR devices have a Clock Prescale Register. On those devices
-without a Clock Prescale Register, these macros are not available.
+Some devices have the XTAL Divide Control Register which offer similar
+functionnality than System Clock Prescale Register.
+
+Below are two macros and an enumerated type that can be used to interface to
+either the Clock Prescale Register or the XTAL Divide Control Register
+depending on your device capability.
+
+\note Not all AVR devices have a Clock Prescale Register or XTAL Divide Control
+Register. On those devices without a Clock Prescale Register or XTAL Divide
+Control Register, these macros are not available.
+
+\note For device using the XTAL Divide Control Register (XDIV), when prescaller
+is used, Timer/Counter0 can only be used in asynchronous mode. Keep in mind
+that Timer/Counter0 source shall be less than ¼th of peripheral clock.
+Therefore, when using a typical 32.768 kHz, one shall not scale the clock
+below 131.072 khz.
+
 */
 
-
 /** \addtogroup avr_power
 \code 
 typedef enum
@@ -1396,8 +1410,25 @@
     clock_div_1_rc = 15, // ATmega128RFA1 only
 } clock_div_t;
 \endcode
-Clock prescaler setting enumerations.
+Clock prescaler setting enumerations for device with System Clock Prescale
+Register (CLKPR).
 
+\code
+typedef enum
+{
+    clock_div_1 = 1,
+    clock_div_2 = 2,
+    clock_div_4 = 4,
+    clock_div_8 = 8,
+    clock_div_16 = 16,
+    clock_div_32 = 32,
+    clock_div_64 = 64,
+    clock_div_128 = 128
+} clock_div_t;
+\endcode
+Clock prescaler setting enumerations for device with XTAL Divide Control
+Register (XDIV).
+
 */
 typedef enum
 {
@@ -1426,6 +1457,11 @@
 optimizations are disabled.
 
 The type of x is clock_div_t.
+
+\note For device with XTAL Divide Control Register (XDIV), x can actually range
+from 1 to 128. Thus, one does not need to use clock_div_t type as argument.
+Remember that gcc will interprete enums as generic type, most likely as
+unsigned char here.
 */
 void clock_prescale_set(clock_div_t __x)
 {
@@ -1447,6 +1483,11 @@
 \code clock_prescale_get() \endcode
 Gets and returns the clock prescaler register setting. The return type is clock_div_t.
 
+\note For device with XTAL Divide Control Register (XDIV), return can actually
+range from 1 to 128. Thus, one does not need to use clock_div_t type as
+argument. Remember that gcc will interprete enums as generic type, most likely
+as unsigned char here.
+
 */
 #define clock_prescale_get()  (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
 
@@ -1506,10 +1547,91 @@
 
 #define clock_prescale_get()  (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
 
+#elif defined(__AVR_ATmega64__) \
+|| defined(__AVR_ATmega103__) \
+|| defined(__AVR_ATmega128__)
 
-#endif
+#include <util/atomic.h>
 
+//Enum is declared for code compatibility
+typedef enum
+{
+    clock_div_1 = 1,
+    clock_div_2 = 2,
+    clock_div_4 = 4,
+    clock_div_8 = 8,
+    clock_div_16 = 16,
+    clock_div_32 = 32,
+    clock_div_64 = 64,
+    clock_div_128 = 128
+} clock_div_t;
 
+void clock_prescale_set(clock_div_t __x)
+{
+    if((__x <= 0) || (__x > 129))
+    {
+        return;//Invalid value.
+    }
+    else
+        {
+        uint8_t __tmp = 0;
+        //Algo explain:
+        //1 - Clear XDIV in order for it to accept a new value (actually only
+        //    XDIVEN need to be cleared, but clearing XDIV is faster than
+        //    read-modify-write since we will rewrite XDIV later anyway).
+        //2 - wait 8 clock cycle for stability
+        //3 - Exist if requested prescaller is 1
+        //4 - Calculate XDIV6..0 value = 129 - __x
+        //5 - Set XDIVEN bit
+        //6 - write XDIV with calculated value
+        //7 - wait 8 clock cycle for stability
+        __asm__ __volatile__ (
+            "in __tmp_reg__,__SREG__" "\n\t"
+            "cli" "\n\t"
+            "out %1, __zero_reg__" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "cpi %0, 0x01" "\n\t"
+            "breq L_%=" "\n\t"
+            "ldi %2, 0x81" "\n\t" //129
+            "sub %2, %0" "\n\t"
+            "ori %2, 0x80" "\n\t" //128
+            "out %1, %2" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "L_%=: " "out __SREG__, __tmp_reg__"
+            : /* no outputs */
+            :"d" (__x),
+             "I" (_SFR_IO_ADDR(XDIV)),
+             "d" (__tmp)
+            : "r0");
+        }
+}
 
+clock_div_t clock_prescale_get(void)
+{
+    if(bit_is_clear(XDIV, XDIVEN))
+    {
+        return 1;
+    }
+    else
+    {
+        return (clock_div_t)(129 - (XDIV & 0x7F));
+    }
+}
 
+#endif
+
 #endif /* _AVR_POWER_H_ */
Index: power.h
===================================================================
--- power.h	(révision 2179)
+++ power.h	(copie de travail)
@@ -1,4 +1,5 @@
 /* Copyright (c) 2006, 2007, 2008  Eric B. Weddington
+   Copyright (c) 2010 Frédéric Nadeau
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -1372,14 +1373,27 @@
 
 Some of the newer AVRs contain a System Clock Prescale Register (CLKPR) that
 allows you to decrease the system clock frequency and the power consumption
-when the need for processing power is low. Below are two macros and an
-enumerated type that can be used to interface to the Clock Prescale Register.
+when the need for processing power is low.
 
-\note Not all AVR devices have a Clock Prescale Register. On those devices
-without a Clock Prescale Register, these macros are not available.
+Some devices have the XTAL Divide Control Register which offer similar
+functionnality than System Clock Prescale Register.
+
+Below are two macros and an enumerated type that can be used to interface to
+either the Clock Prescale Register or the XTAL Divide Control Register
+depending on your device capability.
+
+\note Not all AVR devices have a Clock Prescale Register or XTAL Divide Control
+Register. On those devices without a Clock Prescale Register or XTAL Divide
+Control Register, these macros are not available.
+
+\note For device using the XTAL Divide Control Register (XDIV), when prescaller
+is used, Timer/Counter0 can only be used in asynchronous mode. Keep in mind
+that Timer/Counter0 source shall be less than ¼th of peripheral clock.
+Therefore, when using a typical 32.768 kHz, one shall not scale the clock
+below 131.072 khz.
+
 */
 
-
 /** \addtogroup avr_power
 \code 
 typedef enum
@@ -1396,8 +1410,25 @@
     clock_div_1_rc = 15, // ATmega128RFA1 only
 } clock_div_t;
 \endcode
-Clock prescaler setting enumerations.
+Clock prescaler setting enumerations for device with System Clock Prescale
+Register (CLKPR).
 
+\code
+typedef enum
+{
+    clock_div_1 = 1,
+    clock_div_2 = 2,
+    clock_div_4 = 4,
+    clock_div_8 = 8,
+    clock_div_16 = 16,
+    clock_div_32 = 32,
+    clock_div_64 = 64,
+    clock_div_128 = 128
+} clock_div_t;
+\endcode
+Clock prescaler setting enumerations for device with XTAL Divide Control
+Register (XDIV).
+
 */
 typedef enum
 {
@@ -1426,6 +1457,11 @@
 optimizations are disabled.
 
 The type of x is clock_div_t.
+
+\note For device with XTAL Divide Control Register (XDIV), x can actually range
+from 1 to 128. Thus, one does not need to use clock_div_t type as argument.
+Remember that gcc will interprete enums as generic type, most likely as
+unsigned char here.
 */
 void clock_prescale_set(clock_div_t __x)
 {
@@ -1447,6 +1483,11 @@
 \code clock_prescale_get() \endcode
 Gets and returns the clock prescaler register setting. The return type is clock_div_t.
 
+\note For device with XTAL Divide Control Register (XDIV), return can actually
+range from 1 to 128. Thus, one does not need to use clock_div_t type as
+argument. Remember that gcc will interprete enums as generic type, most likely
+as unsigned char here.
+
 */
 #define clock_prescale_get()  (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
 
@@ -1506,10 +1547,89 @@
 
 #define clock_prescale_get()  (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
 
+#elif defined(__AVR_ATmega64__) \
+|| defined(__AVR_ATmega103__) \
+|| defined(__AVR_ATmega128__)
 
-#endif
+//Enum is declared for code compatibility
+typedef enum
+{
+    clock_div_1 = 1,
+    clock_div_2 = 2,
+    clock_div_4 = 4,
+    clock_div_8 = 8,
+    clock_div_16 = 16,
+    clock_div_32 = 32,
+    clock_div_64 = 64,
+    clock_div_128 = 128
+} clock_div_t;
 
+void clock_prescale_set(clock_div_t __x)
+{
+    if((__x <= 0) || (__x > 129))
+    {
+        return;//Invalid value.
+    }
+    else
+        {
+        uint8_t __tmp = 0;
+        //Algo explained:
+        //1 - Clear XDIV in order for it to accept a new value (actually only
+        //    XDIVEN need to be cleared, but clearing XDIV is faster than
+        //    read-modify-write since we will rewrite XDIV later anyway)
+        //2 - wait 8 clock cycle for stability, see datasheet erreta
+        //3 - Exist if requested prescaller is 1
+        //4 - Calculate XDIV6..0 value = 129 - __x
+        //5 - Set XDIVEN bit in calculated value
+        //6 - write XDIV with calculated value
+        //7 - wait 8 clock cycle for stability, see datasheet erreta
+        __asm__ __volatile__ (
+            "in __tmp_reg__,__SREG__" "\n\t"
+            "cli" "\n\t"
+            "out %1, __zero_reg__" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "cpi %0, 0x01" "\n\t"
+            "breq L_%=" "\n\t"
+            "ldi %2, 0x81" "\n\t" //129
+            "sub %2, %0" "\n\t"
+            "ori %2, 0x80" "\n\t" //128
+            "out %1, %2" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "nop" "\n\t"
+            "L_%=: " "out __SREG__, __tmp_reg__"
+            : /* no outputs */
+            :"d" (__x),
+             "I" (_SFR_IO_ADDR(XDIV)),
+             "d" (__tmp)
+            : "r0");
+        }
+}
 
+clock_div_t clock_prescale_get(void)
+{
+    if(bit_is_clear(XDIV, XDIVEN))
+    {
+        return 1;
+    }
+    else
+    {
+        return (clock_div_t)(129 - (XDIV & 0x7F));
+    }
+}
 
+#endif
 
 #endif /* _AVR_POWER_H_ */
