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private: |
private: |
43 |
PSR psr; |
PSR psr; |
44 |
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enum phase { IF, ID, EX, MA, WB }; |
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vector<bool> phase_active; |
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48 |
// phase 1. IF (instruction fetch) |
// phase 1. IF (instruction fetch) |
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internal_reg nPC; |
internal_reg nPC; |
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cache ICache; |
cache ICache; |
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const4 c4; |
const4 c4; |
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sum Add1; |
sum Add1; |
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55 |
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// phase 2. ID (instruction decode) |
// phase 2. ID (instruction decode) |
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instr_word nOP; |
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internal_reg PC, IR; |
internal_reg PC, IR; |
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registers Registers; |
registers Registers; |
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constant Const; |
constant Const; |
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sum Add2; |
sum Add2; |
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mplexer Mpx1; |
mplexer Mpx1; |
65 |
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// phase 3. EX/AC (execution/address calculation) |
// phase 3. EX/AC (execution/address calculation) |
67 |
instr_word OP; |
instr_word OP; |
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internal_reg pPC, A1, A2, R; |
internal_reg pPC, A1, A2, R; |
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75 |
mplexer Mpx2; |
mplexer Mpx2; |
76 |
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77 |
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78 |
// phase 4. MA (memory access) |
// phase 4. MA (memory access) |
79 |
instr_word pOP; |
instr_word pOP; |
80 |
internal_reg T, pR; |
internal_reg T, pR; |
87 |
internal_reg pT, D; |
internal_reg pT, D; |
88 |
internal_reg ppDR; |
internal_reg ppDR; |
89 |
mplexer Mpx9; |
mplexer Mpx9; |
90 |
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91 |
public: |
public: |
92 |
vmachine( void ); |
vmachine( void ); |
93 |
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94 |
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void init( vector<unsigned long> data, |
95 |
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vector<unsigned long> instr ); |
96 |
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97 |
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void step( void ); |
98 |
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void do_IF( void ); |
99 |
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void do_ID( void ); |
100 |
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void do_EX( void ); |
101 |
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void do_MA( void ); |
102 |
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void do_WB( void ); |
103 |
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104 |
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105 |
int get_CWP(void) { return psr.CWP; } |
int get_CWP(void) { return psr.CWP; } |
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int get_N(void) { return psr.N; } |
int get_N(void) { return psr.N; } |