22 |
|
|
23 |
vmachine::vmachine( void ) : |
vmachine::vmachine( void ) : |
24 |
phase_active(5), |
phase_active(5), |
25 |
|
phase_stall(5), |
26 |
|
|
27 |
nPC(3), |
nPC(3), |
28 |
PC(2), IR(2), Registers(3,3),Const(2), Mpx3(2,1), |
PC(2), IR(2), Registers(3,3),Const(2), Mpx3(2,1), |
159 |
Mpx2.set( 1 ); |
Mpx2.set( 1 ); |
160 |
|
|
161 |
phase_active[IF] = true; |
phase_active[IF] = true; |
162 |
for( int i = ID ; i <= WB ; i++ ) |
phase_stall[IF] = stall_no; |
163 |
|
for( int i = ID ; i <= WB ; i++ ){ |
164 |
phase_active[i] = false; |
phase_active[i] = false; |
165 |
|
phase_stall[i] = stall_no; |
166 |
|
} |
167 |
|
|
168 |
on = true; |
on = true; |
169 |
} |
} |
176 |
|
|
177 |
if (phase_active[WB]) |
if (phase_active[WB]) |
178 |
do_WB(); |
do_WB(); |
179 |
if (phase_active[MA] ) |
if (phase_active[MA]) |
180 |
do_MA(); |
do_MA(); |
181 |
if (phase_active[EX] ) |
if (phase_active[EX]) |
182 |
do_EX(); |
do_EX(); |
183 |
if (phase_active[ID] ) |
if (phase_active[ID]) |
184 |
do_ID(); |
do_ID(); |
185 |
if (phase_active[IF] ) |
if (phase_active[IF] && phase_stall[IF] != stall_jmpl) |
186 |
do_IF(); |
do_IF(); |
187 |
|
|
188 |
|
|
192 |
|
|
193 |
pppsr = ppsr; |
pppsr = ppsr; |
194 |
ppsr = psr; |
ppsr = psr; |
195 |
|
|
196 |
|
do_ADDR(); |
197 |
|
|
198 |
|
// delayed IF phase after processing new |
199 |
|
if (phase_stall[IF] == stall_jmpl){ |
200 |
|
do_IF(); |
201 |
|
// setting mplexer 2. to normal state |
202 |
|
// [was changed by jmpl intruction] |
203 |
|
Mpx2.set(1); |
204 |
|
do_ADDR(); |
205 |
|
phase_stall[IF] = stall_no; |
206 |
|
} |
207 |
|
|
208 |
|
/* |
209 |
|
phase_stall[WB] = phase_stall[MA]; |
210 |
|
phase_stall[MA] = phase_stall[EX]; |
211 |
|
phase_stall[EX] = phase_stall[ID]; |
212 |
|
phase_stall[ID] = phase_stall[IF]; |
213 |
|
phase_stall[IF] = stall_no; |
214 |
|
*/ |
215 |
|
} |
216 |
|
void vmachine::do_ADDR( void ) |
217 |
|
{ |
218 |
c4.process(); |
c4.process(); |
219 |
Add1.process(); |
Add1.process(); |
220 |
Add2.process(); |
Add2.process(); |
221 |
Mpx1.process(); |
Mpx1.process(); |
222 |
Mpx2.process(); |
Mpx2.process(); |
223 |
nPC.remember(); |
nPC.remember(); |
224 |
|
#ifdef VMDEBUG |
225 |
|
cout.form("Address calc: nPC: %08X\n",nPC.get()); |
226 |
|
#endif |
227 |
|
|
228 |
} |
} |
|
|
|
229 |
void vmachine::do_IF( void ) |
void vmachine::do_IF( void ) |
230 |
{ |
{ |
231 |
nPC.pass_through(); |
nPC.pass_through(); |
232 |
ICache.process(cache::rd, cache::word); |
ICache.process(cache::rd, cache::word); |
|
|
|
233 |
PC.remember(); |
PC.remember(); |
234 |
IR.remember(); |
IR.remember(); |
235 |
|
|
236 |
|
if ( IR.get() == 0 ){ /* halt [0] */ |
237 |
|
phase_active[IF] = false; |
238 |
|
return; |
239 |
|
} |
240 |
|
|
241 |
#ifdef VMDEBUG |
#ifdef VMDEBUG |
242 |
cout.form("IF phase: nPC: %08X\n",nPC.get()); |
cout.form("IF phase: nPC: %08X\n",nPC.get()); |
298 |
else |
else |
299 |
Mpx1.set(1); |
Mpx1.set(1); |
300 |
|
|
301 |
|
|
302 |
A1.remember(); |
A1.remember(); |
303 |
A2.remember(); |
A2.remember(); |
304 |
R.remember(); |
R.remember(); |
331 |
|
|
332 |
if ( phase_active[WB] && OP.is_arlog_src() && |
if ( phase_active[WB] && OP.is_arlog_src() && |
333 |
(ppOP.is_arlog_dst() || ppOP.group==instr_word::load) && |
(ppOP.is_arlog_dst() || ppOP.group==instr_word::load) && |
334 |
ppOP.dst == OP.src1 ) |
Registers.real_regnum(pppsr.CWP, ppOP.dst) |
335 |
|
== Registers.real_regnum(psr.CWP, OP.src1) ) |
336 |
Mpx4.process( 3 ); |
Mpx4.process( 3 ); |
337 |
else if ( phase_active[MA] && OP.is_arlog_src() && |
else if ( phase_active[MA] && OP.is_arlog_src() && |
338 |
pOP.is_arlog_dst() && pOP.dst == OP.src1) |
pOP.is_arlog_dst() && |
339 |
|
Registers.real_regnum(ppsr.CWP, pOP.dst) |
340 |
|
== Registers.real_regnum(psr.CWP, OP.src1)) |
341 |
Mpx4.process( 1 ); |
Mpx4.process( 1 ); |
342 |
else if ( phase_active[MA] && OP.is_arlog_src() && |
else if ( phase_active[MA] && OP.is_arlog_src() && |
343 |
pOP.group == instr_word::load && pOP.dst == OP.src1 ) |
pOP.group == instr_word::load && |
344 |
|
Registers.real_regnum(ppsr.CWP, pOP.dst) |
345 |
|
== Registers.real_regnum(psr.CWP,OP.src1) ){ |
346 |
|
// phase_stall[IF] = stall_load; |
347 |
; /* FIXME: stall */ |
; /* FIXME: stall */ |
348 |
else |
} else |
349 |
Mpx4.process( 2 ); |
Mpx4.process( 2 ); |
350 |
|
|
351 |
if ( phase_active[WB] && OP.is_arlog_src() && |
if ( phase_active[WB] && OP.is_arlog_src() && |
352 |
(ppOP.is_arlog_dst() || ppOP.group==instr_word::load) && |
(ppOP.is_arlog_dst() || ppOP.group==instr_word::load) && |
353 |
ppOP.dst == OP.src2 ) |
Registers.real_regnum(pppsr.CWP, ppOP.dst) |
354 |
|
== Registers.real_regnum(psr.CWP, OP.src2) ) |
355 |
Mpx5.process( 3 ); |
Mpx5.process( 3 ); |
356 |
else if ( phase_active[MA] && OP.is_arlog_src() && |
else if ( phase_active[MA] && OP.is_arlog_src() && |
357 |
pOP.is_arlog_dst() && pOP.dst == OP.src2) |
pOP.is_arlog_dst() && |
358 |
|
Registers.real_regnum(ppsr.CWP, pOP.dst) |
359 |
|
== Registers.real_regnum(psr.CWP, OP.src2)) |
360 |
Mpx5.process( 1 ); |
Mpx5.process( 1 ); |
361 |
else if ( phase_active[MA] && OP.is_arlog_src() && |
else if ( phase_active[MA] && OP.is_arlog_src() && |
362 |
pOP.group == instr_word::load && pOP.dst == OP.src2 ) |
pOP.group == instr_word::load && |
363 |
|
Registers.real_regnum(ppsr.CWP, pOP.dst) |
364 |
|
== Registers.real_regnum(psr.CWP, OP.src2) ){ |
365 |
|
// phase_stall[IF] = stall_load; |
366 |
; /* FIXME: stall */ |
; /* FIXME: stall */ |
367 |
else |
} else |
368 |
Mpx5.process( 2 ); |
Mpx5.process( 2 ); |
369 |
|
|
370 |
if ( phase_active[WB] && OP.group == instr_word::store && |
if ( phase_active[WB] && OP.group == instr_word::store && |
371 |
(ppOP.is_arlog_dst() || ppOP.group==instr_word::load) && |
(ppOP.is_arlog_dst() || ppOP.group==instr_word::load) && |
372 |
ppOP.dst == OP.dst ) |
Registers.real_regnum(pppsr.CWP, ppOP.dst) |
373 |
|
== Registers.real_regnum(psr.CWP, OP.dst) ) |
374 |
Mpx7.process( 2 ); |
Mpx7.process( 2 ); |
375 |
else |
else |
376 |
Mpx7.process( 1 ); |
Mpx7.process( 1 ); |
392 |
Mpx6.process(3); |
Mpx6.process(3); |
393 |
else |
else |
394 |
Mpx6.process(2); |
Mpx6.process(2); |
395 |
|
|
396 |
if (OP.instr == instr_word::jmpl){ |
if (OP.instr == instr_word::jmpl){ |
397 |
Mpx2.set(2); |
Mpx2.set(2); |
398 |
|
phase_stall[IF] = stall_jmpl; |
399 |
|
|
400 |
/* FIXME: stall */ |
/* FIXME: stall */ |
401 |
} |
} |
402 |
|
|
432 |
|
|
433 |
if ( phase_active[WB] && pOP.group == instr_word::store && |
if ( phase_active[WB] && pOP.group == instr_word::store && |
434 |
(ppOP.is_arlog_dst() || ppOP.group==instr_word::load) && |
(ppOP.is_arlog_dst() || ppOP.group==instr_word::load) && |
435 |
ppOP.dst == pOP.dst ) |
Registers.real_regnum(pppsr.CWP, ppOP.dst) |
436 |
|
== Registers.real_regnum(ppsr.CWP, pOP.dst) ) |
437 |
Mpx8.process( 2 ); |
Mpx8.process( 2 ); |
438 |
else |
else |
439 |
Mpx8.process( 1 ); |
Mpx8.process( 1 ); |