2328 |
int i; |
int i; |
2329 |
uint32_t tmp; |
uint32_t tmp; |
2330 |
|
|
2331 |
for(i = 1; i < 8; i++) |
for(i = 0; i < 8; i++) |
2332 |
qemu_put_be32s(f, &env->gregs[i]); |
qemu_put_betls(f, &env->gregs[i]); |
2333 |
tmp = env->regwptr - env->regbase; |
for(i = 0; i < NWINDOWS * 16; i++) |
2334 |
qemu_put_be32s(f, &tmp); |
qemu_put_betls(f, &env->regbase[i]); |
|
for(i = 1; i < NWINDOWS * 16 + 8; i++) |
|
|
qemu_put_be32s(f, &env->regbase[i]); |
|
2335 |
|
|
2336 |
/* FPU */ |
/* FPU */ |
2337 |
for(i = 0; i < 32; i++) { |
for(i = 0; i < TARGET_FPREGS; i++) { |
2338 |
uint64_t mant; |
union { |
2339 |
uint16_t exp; |
TARGET_FPREG_T f; |
2340 |
cpu_get_fp64(&mant, &exp, env->fpr[i]); |
target_ulong i; |
2341 |
qemu_put_be64(f, mant); |
} u; |
2342 |
qemu_put_be16(f, exp); |
u.f = env->fpr[i]; |
2343 |
|
qemu_put_betl(f, u.i); |
2344 |
} |
} |
2345 |
qemu_put_be32s(f, &env->pc); |
|
2346 |
qemu_put_be32s(f, &env->npc); |
qemu_put_betls(f, &env->pc); |
2347 |
qemu_put_be32s(f, &env->y); |
qemu_put_betls(f, &env->npc); |
2348 |
|
qemu_put_betls(f, &env->y); |
2349 |
tmp = GET_PSR(env); |
tmp = GET_PSR(env); |
2350 |
qemu_put_be32s(f, &tmp); |
qemu_put_be32(f, tmp); |
2351 |
qemu_put_be32s(f, &env->fsr); |
qemu_put_be32s(f, &env->fsr); |
|
qemu_put_be32s(f, &env->cwp); |
|
2352 |
qemu_put_be32s(f, &env->wim); |
qemu_put_be32s(f, &env->wim); |
2353 |
qemu_put_be32s(f, &env->tbr); |
qemu_put_be32s(f, &env->tbr); |
2354 |
/* MMU */ |
/* MMU */ |
2362 |
int i; |
int i; |
2363 |
uint32_t tmp; |
uint32_t tmp; |
2364 |
|
|
2365 |
for(i = 1; i < 8; i++) |
for(i = 0; i < 8; i++) |
2366 |
qemu_get_be32s(f, &env->gregs[i]); |
qemu_get_betls(f, &env->gregs[i]); |
2367 |
qemu_get_be32s(f, &tmp); |
for(i = 0; i < NWINDOWS * 16; i++) |
2368 |
env->regwptr = env->regbase + tmp; |
qemu_get_betls(f, &env->regbase[i]); |
|
for(i = 1; i < NWINDOWS * 16 + 8; i++) |
|
|
qemu_get_be32s(f, &env->regbase[i]); |
|
2369 |
|
|
2370 |
/* FPU */ |
/* FPU */ |
2371 |
for(i = 0; i < 32; i++) { |
for(i = 0; i < TARGET_FPREGS; i++) { |
2372 |
uint64_t mant; |
union { |
2373 |
uint16_t exp; |
TARGET_FPREG_T f; |
2374 |
|
target_ulong i; |
2375 |
qemu_get_be64s(f, &mant); |
} u; |
2376 |
qemu_get_be16s(f, &exp); |
u.i = qemu_get_betl(f); |
2377 |
env->fpr[i] = cpu_put_fp64(mant, exp); |
env->fpr[i] = u.f; |
2378 |
} |
} |
2379 |
qemu_get_be32s(f, &env->pc); |
|
2380 |
qemu_get_be32s(f, &env->npc); |
qemu_get_betls(f, &env->pc); |
2381 |
qemu_get_be32s(f, &env->y); |
qemu_get_betls(f, &env->npc); |
2382 |
qemu_get_be32s(f, &tmp); |
qemu_get_betls(f, &env->y); |
2383 |
|
tmp = qemu_get_be32(f); |
2384 |
|
env->cwp = 0; /* needed to ensure that the wrapping registers are |
2385 |
|
correctly updated */ |
2386 |
PUT_PSR(env, tmp); |
PUT_PSR(env, tmp); |
2387 |
qemu_get_be32s(f, &env->fsr); |
qemu_get_be32s(f, &env->fsr); |
|
qemu_get_be32s(f, &env->cwp); |
|
2388 |
qemu_get_be32s(f, &env->wim); |
qemu_get_be32s(f, &env->wim); |
2389 |
qemu_get_be32s(f, &env->tbr); |
qemu_get_be32s(f, &env->tbr); |
2390 |
/* MMU */ |
/* MMU */ |
2391 |
for(i = 0; i < 16; i++) |
for(i = 0; i < 16; i++) |
2392 |
qemu_get_be32s(f, &env->mmuregs[i]); |
qemu_get_be32s(f, &env->mmuregs[i]); |
2393 |
|
|
2394 |
tlb_flush(env, 1); |
tlb_flush(env, 1); |
2395 |
return 0; |
return 0; |
2396 |
} |
} |