2214 |
#elif defined(TARGET_SPARC) |
#elif defined(TARGET_SPARC) |
2215 |
void cpu_save(QEMUFile *f, void *opaque) |
void cpu_save(QEMUFile *f, void *opaque) |
2216 |
{ |
{ |
2217 |
|
CPUState *env = opaque; |
2218 |
|
int i; |
2219 |
|
uint32_t tmp; |
2220 |
|
|
2221 |
|
for(i = 1; i < 8; i++) |
2222 |
|
qemu_put_be32s(f, &env->gregs[i]); |
2223 |
|
tmp = env->regwptr - env->regbase; |
2224 |
|
qemu_put_be32s(f, &tmp); |
2225 |
|
for(i = 1; i < NWINDOWS * 16 + 8; i++) |
2226 |
|
qemu_put_be32s(f, &env->regbase[i]); |
2227 |
|
|
2228 |
|
/* FPU */ |
2229 |
|
for(i = 0; i < 32; i++) { |
2230 |
|
uint64_t mant; |
2231 |
|
uint16_t exp; |
2232 |
|
cpu_get_fp64(&mant, &exp, env->fpr[i]); |
2233 |
|
qemu_put_be64(f, mant); |
2234 |
|
qemu_put_be16(f, exp); |
2235 |
|
} |
2236 |
|
qemu_put_be32s(f, &env->pc); |
2237 |
|
qemu_put_be32s(f, &env->npc); |
2238 |
|
qemu_put_be32s(f, &env->y); |
2239 |
|
tmp = GET_PSR(env); |
2240 |
|
qemu_put_be32s(f, &tmp); |
2241 |
|
qemu_put_be32s(f, &env->fsr); |
2242 |
|
qemu_put_be32s(f, &env->cwp); |
2243 |
|
qemu_put_be32s(f, &env->wim); |
2244 |
|
qemu_put_be32s(f, &env->tbr); |
2245 |
|
/* MMU */ |
2246 |
|
for(i = 0; i < 16; i++) |
2247 |
|
qemu_put_be32s(f, &env->mmuregs[i]); |
2248 |
} |
} |
2249 |
|
|
2250 |
int cpu_load(QEMUFile *f, void *opaque, int version_id) |
int cpu_load(QEMUFile *f, void *opaque, int version_id) |
2251 |
{ |
{ |
2252 |
|
CPUState *env = opaque; |
2253 |
|
int i; |
2254 |
|
uint32_t tmp; |
2255 |
|
|
2256 |
|
for(i = 1; i < 8; i++) |
2257 |
|
qemu_get_be32s(f, &env->gregs[i]); |
2258 |
|
qemu_get_be32s(f, &tmp); |
2259 |
|
env->regwptr = env->regbase + tmp; |
2260 |
|
for(i = 1; i < NWINDOWS * 16 + 8; i++) |
2261 |
|
qemu_get_be32s(f, &env->regbase[i]); |
2262 |
|
|
2263 |
|
/* FPU */ |
2264 |
|
for(i = 0; i < 32; i++) { |
2265 |
|
uint64_t mant; |
2266 |
|
uint16_t exp; |
2267 |
|
|
2268 |
|
qemu_get_be64s(f, &mant); |
2269 |
|
qemu_get_be16s(f, &exp); |
2270 |
|
env->fpr[i] = cpu_put_fp64(mant, exp); |
2271 |
|
} |
2272 |
|
qemu_get_be32s(f, &env->pc); |
2273 |
|
qemu_get_be32s(f, &env->npc); |
2274 |
|
qemu_get_be32s(f, &env->y); |
2275 |
|
qemu_get_be32s(f, &tmp); |
2276 |
|
PUT_PSR(env, tmp); |
2277 |
|
qemu_get_be32s(f, &env->fsr); |
2278 |
|
qemu_get_be32s(f, &env->cwp); |
2279 |
|
qemu_get_be32s(f, &env->wim); |
2280 |
|
qemu_get_be32s(f, &env->tbr); |
2281 |
|
/* MMU */ |
2282 |
|
for(i = 0; i < 16; i++) |
2283 |
|
qemu_get_be32s(f, &env->mmuregs[i]); |
2284 |
|
tlb_flush(env, 1); |
2285 |
return 0; |
return 0; |
2286 |
} |
} |
2287 |
#else |
#else |
2452 |
|
|
2453 |
static void main_cpu_reset(void *opaque) |
static void main_cpu_reset(void *opaque) |
2454 |
{ |
{ |
2455 |
#ifdef TARGET_I386 |
#if defined(TARGET_I386) || defined(TARGET_SPARC) |
2456 |
CPUState *env = opaque; |
CPUState *env = opaque; |
2457 |
cpu_reset(env); |
cpu_reset(env); |
2458 |
#endif |
#endif |