/[qemu]/qemu/translate-i386.c
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Diff of /qemu/translate-i386.c

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revision 1.57 by bellard, Sun Aug 10 21:41:46 2003 UTC revision 1.58 by bellard, Wed Aug 20 23:02:09 2003 UTC
# Line 1552  static void gen_movl_seg_T0(DisasContext Line 1552  static void gen_movl_seg_T0(DisasContext
1552      else      else
1553          gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));          gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
1554      /* abort translation because the register may have a non zero base      /* abort translation because the register may have a non zero base
1555         or because ss32 may change */         or because ss32 may change. For R_SS, translation must always
1556           stop as a special handling must be done to disable hardware
1557           interrupts for the next instruction */
1558      if (seg_reg == R_SS || (!s->addseg && seg_reg < R_FS))      if (seg_reg == R_SS || (!s->addseg && seg_reg < R_FS))
1559          s->is_jmp = 2;          s->is_jmp = 2;
1560  }  }
# Line 2356  long disas_insn(DisasContext *s, uint8_t Line 2358  long disas_insn(DisasContext *s, uint8_t
2358      case 0x07: /* pop es */      case 0x07: /* pop es */
2359      case 0x17: /* pop ss */      case 0x17: /* pop ss */
2360      case 0x1f: /* pop ds */      case 0x1f: /* pop ds */
2361            reg = b >> 3;
2362          gen_pop_T0(s);          gen_pop_T0(s);
2363          gen_movl_seg_T0(s, b >> 3, pc_start - s->cs_base);          gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
2364          gen_pop_update(s);          gen_pop_update(s);
2365          /* XXX: if reg == SS, inhibit interrupts/trace */          if (reg == R_SS) {
2366                /* if reg == SS, inhibit interrupts/trace */
2367                gen_op_set_inhibit_irq();
2368            }
2369          break;          break;
2370      case 0x1a1: /* pop fs */      case 0x1a1: /* pop fs */
2371      case 0x1a9: /* pop gs */      case 0x1a9: /* pop gs */
# Line 2418  long disas_insn(DisasContext *s, uint8_t Line 2424  long disas_insn(DisasContext *s, uint8_t
2424              goto illegal_op;              goto illegal_op;
2425          gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);          gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
2426          gen_movl_seg_T0(s, reg, pc_start - s->cs_base);          gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
2427          /* XXX: if reg == SS, inhibit interrupts/trace */          if (reg == R_SS) {
2428                /* if reg == SS, inhibit interrupts/trace */
2429                gen_op_set_inhibit_irq();
2430            }
2431          break;          break;
2432      case 0x8c: /* mov Gv, seg */      case 0x8c: /* mov Gv, seg */
2433          modrm = ldub(s->pc++);          modrm = ldub(s->pc++);
# Line 3704  long disas_insn(DisasContext *s, uint8_t Line 3713  long disas_insn(DisasContext *s, uint8_t
3713          if (!s->vm86) {          if (!s->vm86) {
3714              if (s->cpl <= s->iopl) {              if (s->cpl <= s->iopl) {
3715                  gen_op_sti();                  gen_op_sti();
3716                    /* interruptions are enabled only the first insn after sti */
3717                    gen_op_set_inhibit_irq();
3718                  s->is_jmp = 2; /* give a chance to handle pending irqs */                  s->is_jmp = 2; /* give a chance to handle pending irqs */
3719              } else {              } else {
3720                  gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);                  gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
# Line 3711  long disas_insn(DisasContext *s, uint8_t Line 3722  long disas_insn(DisasContext *s, uint8_t
3722          } else {          } else {
3723              if (s->iopl == 3) {              if (s->iopl == 3) {
3724                  gen_op_sti();                  gen_op_sti();
3725                    /* interruptions are enabled only the first insn after sti */
3726                    gen_op_set_inhibit_irq();
3727                  s->is_jmp = 2; /* give a chance to handle pending irqs */                  s->is_jmp = 2; /* give a chance to handle pending irqs */
3728              } else {              } else {
3729                  gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);                  gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3730              }              }
3731          }          }
         /* XXX: interruptions are enabled only the first insn after sti */  
3732          break;          break;
3733      case 0x62: /* bound */      case 0x62: /* bound */
3734          ot = dflag ? OT_LONG : OT_WORD;          ot = dflag ? OT_LONG : OT_WORD;
# Line 4380  static inline int gen_intermediate_code_ Line 4392  static inline int gen_intermediate_code_
4392      flags = tb->flags;      flags = tb->flags;
4393                
4394      dc->pe = env->cr[0] & CR0_PE_MASK;      dc->pe = env->cr[0] & CR0_PE_MASK;
4395      dc->code32 = (flags >> GEN_FLAG_CODE32_SHIFT) & 1;      dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
4396      dc->ss32 = (flags >> GEN_FLAG_SS32_SHIFT) & 1;      dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
4397      dc->addseg = (flags >> GEN_FLAG_ADDSEG_SHIFT) & 1;      dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
4398      dc->f_st = (flags >> GEN_FLAG_ST_SHIFT) & 7;      dc->f_st = 0;
4399      dc->vm86 = (flags >> GEN_FLAG_VM_SHIFT) & 1;      dc->vm86 = (flags >> VM_SHIFT) & 1;
4400      dc->cpl = (flags >> GEN_FLAG_CPL_SHIFT) & 3;      dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
4401      dc->iopl = (flags >> GEN_FLAG_IOPL_SHIFT) & 3;      dc->iopl = (flags >> IOPL_SHIFT) & 3;
4402      dc->tf = (flags >> GEN_FLAG_TF_SHIFT) & 1;      dc->tf = (flags >> TF_SHIFT) & 1;
4403      dc->cc_op = CC_OP_DYNAMIC;      dc->cc_op = CC_OP_DYNAMIC;
4404      dc->cs_base = cs_base;      dc->cs_base = cs_base;
4405      dc->tb = tb;      dc->tb = tb;
4406      dc->popl_esp_hack = 0;      dc->popl_esp_hack = 0;
4407      /* select memory access functions */      /* select memory access functions */
4408      dc->mem_index = 0;      dc->mem_index = 0;
4409      if ((flags >> GEN_FLAG_SOFT_MMU_SHIFT) & 1) {      if (flags & HF_SOFTMMU_MASK) {
4410          if (dc->cpl == 3)          if (dc->cpl == 3)
4411              dc->mem_index = 6;              dc->mem_index = 6;
4412          else          else
# Line 4408  static inline int gen_intermediate_code_ Line 4420  static inline int gen_intermediate_code_
4420      dc->is_jmp = DISAS_NEXT;      dc->is_jmp = DISAS_NEXT;
4421      pc_ptr = pc_start;      pc_ptr = pc_start;
4422      lj = -1;      lj = -1;
4423    
4424        /* if irq were inhibited for the next instruction, we can disable
4425           them here as it is simpler (otherwise jumps would have to
4426           handled as special case) */
4427        if (flags & HF_INHIBIT_IRQ_MASK) {
4428            gen_op_reset_inhibit_irq();
4429        }
4430      do {      do {
4431          if (env->nb_breakpoints > 0) {          if (env->nb_breakpoints > 0) {
4432              for(j = 0; j < env->nb_breakpoints; j++) {              for(j = 0; j < env->nb_breakpoints; j++) {

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