1575 |
switch(f) { |
switch(f) { |
1576 |
case 0: /* OP Ev, Gv */ |
case 0: /* OP Ev, Gv */ |
1577 |
modrm = ldub(s->pc++); |
modrm = ldub(s->pc++); |
1578 |
reg = ((modrm >> 3) & 7) + OR_EAX; |
reg = ((modrm >> 3) & 7); |
1579 |
mod = (modrm >> 6) & 3; |
mod = (modrm >> 6) & 3; |
1580 |
rm = modrm & 7; |
rm = modrm & 7; |
1581 |
if (mod != 3) { |
if (mod != 3) { |
1582 |
gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
1583 |
opreg = OR_TMP0; |
opreg = OR_TMP0; |
1584 |
|
} else if (op == OP_XORL && rm == reg) { |
1585 |
|
xor_zero: |
1586 |
|
/* xor reg, reg optimisation */ |
1587 |
|
gen_op_movl_T0_0(); |
1588 |
|
s->cc_op = CC_OP_LOGICB + ot; |
1589 |
|
gen_op_mov_reg_T0[ot][reg](); |
1590 |
|
gen_op_update1_cc(); |
1591 |
|
break; |
1592 |
} else { |
} else { |
1593 |
opreg = OR_EAX + rm; |
opreg = rm; |
1594 |
} |
} |
1595 |
gen_op_mov_TN_reg[ot][1][reg](); |
gen_op_mov_TN_reg[ot][1][reg](); |
1596 |
gen_op(s, op, ot, opreg); |
gen_op(s, op, ot, opreg); |
1598 |
case 1: /* OP Gv, Ev */ |
case 1: /* OP Gv, Ev */ |
1599 |
modrm = ldub(s->pc++); |
modrm = ldub(s->pc++); |
1600 |
mod = (modrm >> 6) & 3; |
mod = (modrm >> 6) & 3; |
1601 |
reg = ((modrm >> 3) & 7) + OR_EAX; |
reg = ((modrm >> 3) & 7); |
1602 |
rm = modrm & 7; |
rm = modrm & 7; |
1603 |
if (mod != 3) { |
if (mod != 3) { |
1604 |
gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
1605 |
gen_op_ld_T1_A0[ot](); |
gen_op_ld_T1_A0[ot](); |
1606 |
|
} else if (op == OP_XORL && rm == reg) { |
1607 |
|
goto xor_zero; |
1608 |
} else { |
} else { |
1609 |
gen_op_mov_TN_reg[ot][1][rm](); |
gen_op_mov_TN_reg[ot][1][rm](); |
1610 |
} |
} |
3474 |
gen_op_loop[s->aflag][b & 3](val, next_eip); |
gen_op_loop[s->aflag][b & 3](val, next_eip); |
3475 |
s->is_jmp = 1; |
s->is_jmp = 1; |
3476 |
break; |
break; |
3477 |
|
case 0x130: /* wrmsr */ |
3478 |
|
case 0x132: /* rdmsr */ |
3479 |
|
if (s->cpl != 0) { |
3480 |
|
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
3481 |
|
} else { |
3482 |
|
if (b & 2) |
3483 |
|
gen_op_rdmsr(); |
3484 |
|
else |
3485 |
|
gen_op_wrmsr(); |
3486 |
|
} |
3487 |
|
break; |
3488 |
case 0x131: /* rdtsc */ |
case 0x131: /* rdtsc */ |
3489 |
gen_op_rdtsc(); |
gen_op_rdtsc(); |
3490 |
break; |
break; |
4288 |
void cpu_x86_update_cr3(CPUX86State *env) |
void cpu_x86_update_cr3(CPUX86State *env) |
4289 |
{ |
{ |
4290 |
if (env->cr[0] & CR0_PG_MASK) { |
if (env->cr[0] & CR0_PG_MASK) { |
4291 |
#ifdef DEBUG_MMU |
#if defined(DEBUG_MMU) |
4292 |
printf("CR3 update: CR3=%08x\n", env->cr[3]); |
printf("CR3 update: CR3=%08x\n", env->cr[3]); |
4293 |
#endif |
#endif |
4294 |
page_unmap(); |
page_unmap(); |