/[qemu]/qemu/translate-i386.c
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Diff of /qemu/translate-i386.c

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revision 1.46 by bellard, Mon Jun 30 13:12:32 2003 UTC revision 1.47 by bellard, Mon Jun 30 23:36:57 2003 UTC
# Line 390  static GenOpFunc *gen_op_arithc_T0_T1_cc Line 390  static GenOpFunc *gen_op_arithc_T0_T1_cc
390      },      },
391  };  };
392    
393    static GenOpFunc *gen_op_arithc_mem_T0_T1_cc[3][2] = {
394        [OT_BYTE] = {
395            gen_op_adcb_mem_T0_T1_cc,
396            gen_op_sbbb_mem_T0_T1_cc,
397        },
398        [OT_WORD] = {
399            gen_op_adcw_mem_T0_T1_cc,
400            gen_op_sbbw_mem_T0_T1_cc,
401        },
402        [OT_LONG] = {
403            gen_op_adcl_mem_T0_T1_cc,
404            gen_op_sbbl_mem_T0_T1_cc,
405        },
406    };
407    
408  static const int cc_op_arithb[8] = {  static const int cc_op_arithb[8] = {
409      CC_OP_ADDB,      CC_OP_ADDB,
410      CC_OP_LOGICB,      CC_OP_LOGICB,
# Line 407  static GenOpFunc *gen_op_cmpxchg_T0_T1_E Line 422  static GenOpFunc *gen_op_cmpxchg_T0_T1_E
422      gen_op_cmpxchgl_T0_T1_EAX_cc,      gen_op_cmpxchgl_T0_T1_EAX_cc,
423  };  };
424    
425    static GenOpFunc *gen_op_cmpxchg_mem_T0_T1_EAX_cc[3] = {
426        gen_op_cmpxchgb_mem_T0_T1_EAX_cc,
427        gen_op_cmpxchgw_mem_T0_T1_EAX_cc,
428        gen_op_cmpxchgl_mem_T0_T1_EAX_cc,
429    };
430    
431  static GenOpFunc *gen_op_shift_T0_T1_cc[3][8] = {  static GenOpFunc *gen_op_shift_T0_T1_cc[3][8] = {
432      [OT_BYTE] = {      [OT_BYTE] = {
433          gen_op_rolb_T0_T1_cc,          gen_op_rolb_T0_T1_cc,
# Line 440  static GenOpFunc *gen_op_shift_T0_T1_cc[ Line 461  static GenOpFunc *gen_op_shift_T0_T1_cc[
461      },      },
462  };  };
463    
464    static GenOpFunc *gen_op_shift_mem_T0_T1_cc[3][8] = {
465        [OT_BYTE] = {
466            gen_op_rolb_mem_T0_T1_cc,
467            gen_op_rorb_mem_T0_T1_cc,
468            gen_op_rclb_mem_T0_T1_cc,
469            gen_op_rcrb_mem_T0_T1_cc,
470            gen_op_shlb_mem_T0_T1_cc,
471            gen_op_shrb_mem_T0_T1_cc,
472            gen_op_shlb_mem_T0_T1_cc,
473            gen_op_sarb_mem_T0_T1_cc,
474        },
475        [OT_WORD] = {
476            gen_op_rolw_mem_T0_T1_cc,
477            gen_op_rorw_mem_T0_T1_cc,
478            gen_op_rclw_mem_T0_T1_cc,
479            gen_op_rcrw_mem_T0_T1_cc,
480            gen_op_shlw_mem_T0_T1_cc,
481            gen_op_shrw_mem_T0_T1_cc,
482            gen_op_shlw_mem_T0_T1_cc,
483            gen_op_sarw_mem_T0_T1_cc,
484        },
485        [OT_LONG] = {
486            gen_op_roll_mem_T0_T1_cc,
487            gen_op_rorl_mem_T0_T1_cc,
488            gen_op_rcll_mem_T0_T1_cc,
489            gen_op_rcrl_mem_T0_T1_cc,
490            gen_op_shll_mem_T0_T1_cc,
491            gen_op_shrl_mem_T0_T1_cc,
492            gen_op_shll_mem_T0_T1_cc,
493            gen_op_sarl_mem_T0_T1_cc,
494        },
495    };
496    
497  static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[2][2] = {  static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[2][2] = {
498      [0] = {      [0] = {
499          gen_op_shldw_T0_T1_im_cc,          gen_op_shldw_T0_T1_im_cc,
# Line 462  static GenOpFunc *gen_op_shiftd_T0_T1_EC Line 516  static GenOpFunc *gen_op_shiftd_T0_T1_EC
516      },      },
517  };  };
518    
519    static GenOpFunc1 *gen_op_shiftd_mem_T0_T1_im_cc[2][2] = {
520        [0] = {
521            gen_op_shldw_mem_T0_T1_im_cc,
522            gen_op_shrdw_mem_T0_T1_im_cc,
523        },
524        [1] = {
525            gen_op_shldl_mem_T0_T1_im_cc,
526            gen_op_shrdl_mem_T0_T1_im_cc,
527        },
528    };
529    
530    static GenOpFunc *gen_op_shiftd_mem_T0_T1_ECX_cc[2][2] = {
531        [0] = {
532            gen_op_shldw_mem_T0_T1_ECX_cc,
533            gen_op_shrdw_mem_T0_T1_ECX_cc,
534        },
535        [1] = {
536            gen_op_shldl_mem_T0_T1_ECX_cc,
537            gen_op_shrdl_mem_T0_T1_ECX_cc,
538        },
539    };
540    
541  static GenOpFunc *gen_op_btx_T0_T1_cc[2][4] = {  static GenOpFunc *gen_op_btx_T0_T1_cc[2][4] = {
542      [0] = {      [0] = {
543          gen_op_btw_T0_T1_cc,          gen_op_btw_T0_T1_cc,
# Line 763  static void gen_op(DisasContext *s1, int Line 839  static void gen_op(DisasContext *s1, int
839      case OP_SBBL:      case OP_SBBL:
840          if (s1->cc_op != CC_OP_DYNAMIC)          if (s1->cc_op != CC_OP_DYNAMIC)
841              gen_op_set_cc_op(s1->cc_op);              gen_op_set_cc_op(s1->cc_op);
842          gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();          if (d != OR_TMP0) {
843                gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
844                gen_op_mov_reg_T0[ot][d]();
845            } else {
846                gen_op_arithc_mem_T0_T1_cc[ot][op - OP_ADCL]();
847            }
848          s1->cc_op = CC_OP_DYNAMIC;          s1->cc_op = CC_OP_DYNAMIC;
849          /* XXX: incorrect: CC_OP must also be modified AFTER memory access */          goto the_end;
         gen_update_cc = gen_op_update2_cc;  
         break;  
850      case OP_ADDL:      case OP_ADDL:
851          gen_op_addl_T0_T1();          gen_op_addl_T0_T1();
852          s1->cc_op = CC_OP_ADDB + ot;          s1->cc_op = CC_OP_ADDB + ot;
# Line 802  static void gen_op(DisasContext *s1, int Line 881  static void gen_op(DisasContext *s1, int
881         exception support) */         exception support) */
882      if (gen_update_cc)      if (gen_update_cc)
883          gen_update_cc();          gen_update_cc();
884     the_end: ;
885  }  }
886    
887  /* if d == OR_TMP0, it means memory operand (address in A0) */  /* if d == OR_TMP0, it means memory operand (address in A0) */
# Line 831  static void gen_shift(DisasContext *s1, Line 911  static void gen_shift(DisasContext *s1,
911  {  {
912      if (d != OR_TMP0)      if (d != OR_TMP0)
913          gen_op_mov_TN_reg[ot][0][d]();          gen_op_mov_TN_reg[ot][0][d]();
914        else
915            gen_op_ld_T0_A0[ot]();
916      if (s != OR_TMP1)      if (s != OR_TMP1)
917          gen_op_mov_TN_reg[ot][1][s]();          gen_op_mov_TN_reg[ot][1][s]();
918      /* for zero counts, flags are not updated, so must do it dynamically */      /* for zero counts, flags are not updated, so must do it dynamically */
919      if (s1->cc_op != CC_OP_DYNAMIC)      if (s1->cc_op != CC_OP_DYNAMIC)
920          gen_op_set_cc_op(s1->cc_op);          gen_op_set_cc_op(s1->cc_op);
921        
922      gen_op_shift_T0_T1_cc[ot][op]();      if (d != OR_TMP0)
923            gen_op_shift_T0_T1_cc[ot][op]();
924        else
925            gen_op_shift_mem_T0_T1_cc[ot][op]();
926      if (d != OR_TMP0)      if (d != OR_TMP0)
927          gen_op_mov_reg_T0[ot][d]();          gen_op_mov_reg_T0[ot][d]();
928      s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */      s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
# Line 1885  long disas_insn(DisasContext *s, uint8_t Line 1969  long disas_insn(DisasContext *s, uint8_t
1969          } else {          } else {
1970              gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);              gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1971              gen_op_ld_T0_A0[ot]();              gen_op_ld_T0_A0[ot]();
1972              gen_op_cmpxchg_T0_T1_EAX_cc[ot]();              gen_op_cmpxchg_mem_T0_T1_EAX_cc[ot]();
             gen_op_st_T0_A0[ot]();  
1973          }          }
1974          s->cc_op = CC_OP_SUBB + ot;          s->cc_op = CC_OP_SUBB + ot;
1975          break;          break;
# Line 2264  long disas_insn(DisasContext *s, uint8_t Line 2347  long disas_insn(DisasContext *s, uint8_t
2347                            
2348              if (mod != 3) {              if (mod != 3) {
2349                  gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);                  gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
                 gen_op_ld_T0_A0[ot]();  
2350                  opreg = OR_TMP0;                  opreg = OR_TMP0;
2351              } else {              } else {
2352                  opreg = rm + OR_EAX;                  opreg = rm + OR_EAX;
# Line 2279  long disas_insn(DisasContext *s, uint8_t Line 2361  long disas_insn(DisasContext *s, uint8_t
2361                  }                  }
2362                  gen_shifti(s, op, ot, opreg, shift);                  gen_shifti(s, op, ot, opreg, shift);
2363              }              }
   
             if (mod != 3) {  
                 gen_op_st_T0_A0[ot]();  
             }  
2364          }          }
2365          break;          break;
2366      case 0xd0:      case 0xd0:
# Line 2330  long disas_insn(DisasContext *s, uint8_t Line 2408  long disas_insn(DisasContext *s, uint8_t
2408              val = ldub(s->pc++);              val = ldub(s->pc++);
2409              val &= 0x1f;              val &= 0x1f;
2410              if (val) {              if (val) {
2411                  gen_op_shiftd_T0_T1_im_cc[ot - OT_WORD][op](val);                  if (mod == 3)
2412                        gen_op_shiftd_T0_T1_im_cc[ot - OT_WORD][op](val);
2413                    else
2414                        gen_op_shiftd_mem_T0_T1_im_cc[ot - OT_WORD][op](val);
2415                  if (op == 0 && ot != OT_WORD)                  if (op == 0 && ot != OT_WORD)
2416                      s->cc_op = CC_OP_SHLB + ot;                      s->cc_op = CC_OP_SHLB + ot;
2417                  else                  else
# Line 2339  long disas_insn(DisasContext *s, uint8_t Line 2420  long disas_insn(DisasContext *s, uint8_t
2420          } else {          } else {
2421              if (s->cc_op != CC_OP_DYNAMIC)              if (s->cc_op != CC_OP_DYNAMIC)
2422                  gen_op_set_cc_op(s->cc_op);                  gen_op_set_cc_op(s->cc_op);
2423              gen_op_shiftd_T0_T1_ECX_cc[ot - OT_WORD][op]();              if (mod == 3)
2424                    gen_op_shiftd_T0_T1_ECX_cc[ot - OT_WORD][op]();
2425                else
2426                    gen_op_shiftd_mem_T0_T1_ECX_cc[ot - OT_WORD][op]();
2427              s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */              s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2428          }          }
2429          if (mod != 3) {          if (mod == 3) {
             gen_op_st_T0_A0[ot]();  
         } else {  
2430              gen_op_mov_reg_T0[ot][rm]();              gen_op_mov_reg_T0[ot][rm]();
2431          }          }
2432          break;          break;
# Line 3202  long disas_insn(DisasContext *s, uint8_t Line 3284  long disas_insn(DisasContext *s, uint8_t
3284                  gen_op_st_T0_A0[ot]();                  gen_op_st_T0_A0[ot]();
3285              else              else
3286                  gen_op_mov_reg_T0[ot][rm]();                  gen_op_mov_reg_T0[ot][rm]();
3287                gen_op_update_bt_cc();
3288          }          }
3289          break;          break;
3290      case 0x1a3: /* bt Gv, Ev */      case 0x1a3: /* bt Gv, Ev */
# Line 3240  long disas_insn(DisasContext *s, uint8_t Line 3323  long disas_insn(DisasContext *s, uint8_t
3323                  gen_op_st_T0_A0[ot]();                  gen_op_st_T0_A0[ot]();
3324              else              else
3325                  gen_op_mov_reg_T0[ot][rm]();                  gen_op_mov_reg_T0[ot][rm]();
3326                gen_op_update_bt_cc();
3327          }          }
3328          break;          break;
3329      case 0x1bc: /* bsf */      case 0x1bc: /* bsf */
# Line 3640  static uint16_t opc_read_flags[NB_OPS] = Line 3724  static uint16_t opc_read_flags[NB_OPS] =
3724      [INDEX_op_sbbw_T0_T1_cc] = CC_C,      [INDEX_op_sbbw_T0_T1_cc] = CC_C,
3725      [INDEX_op_sbbl_T0_T1_cc] = CC_C,      [INDEX_op_sbbl_T0_T1_cc] = CC_C,
3726    
3727        [INDEX_op_adcb_mem_T0_T1_cc] = CC_C,
3728        [INDEX_op_adcw_mem_T0_T1_cc] = CC_C,
3729        [INDEX_op_adcl_mem_T0_T1_cc] = CC_C,
3730        [INDEX_op_sbbb_mem_T0_T1_cc] = CC_C,
3731        [INDEX_op_sbbw_mem_T0_T1_cc] = CC_C,
3732        [INDEX_op_sbbl_mem_T0_T1_cc] = CC_C,
3733    
3734      /* subtle: due to the incl/decl implementation, C is used */      /* subtle: due to the incl/decl implementation, C is used */
3735      [INDEX_op_update_inc_cc] = CC_C,      [INDEX_op_update_inc_cc] = CC_C,
3736    
# Line 3717  static uint16_t opc_read_flags[NB_OPS] = Line 3808  static uint16_t opc_read_flags[NB_OPS] =
3808      [INDEX_op_rcrb_T0_T1_cc] = CC_C,      [INDEX_op_rcrb_T0_T1_cc] = CC_C,
3809      [INDEX_op_rcrw_T0_T1_cc] = CC_C,      [INDEX_op_rcrw_T0_T1_cc] = CC_C,
3810      [INDEX_op_rcrl_T0_T1_cc] = CC_C,      [INDEX_op_rcrl_T0_T1_cc] = CC_C,
3811    
3812        [INDEX_op_rclb_mem_T0_T1_cc] = CC_C,
3813        [INDEX_op_rclw_mem_T0_T1_cc] = CC_C,
3814        [INDEX_op_rcll_mem_T0_T1_cc] = CC_C,
3815        [INDEX_op_rcrb_mem_T0_T1_cc] = CC_C,
3816        [INDEX_op_rcrw_mem_T0_T1_cc] = CC_C,
3817        [INDEX_op_rcrl_mem_T0_T1_cc] = CC_C,
3818  };  };
3819    
3820  /* flags written by an operation */  /* flags written by an operation */
3821  static uint16_t opc_write_flags[NB_OPS] = {  static uint16_t opc_write_flags[NB_OPS] = {
3822      [INDEX_op_update2_cc] = CC_OSZAPC,      [INDEX_op_update2_cc] = CC_OSZAPC,
3823      [INDEX_op_update1_cc] = CC_OSZAPC,      [INDEX_op_update1_cc] = CC_OSZAPC,
3824        [INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
3825        [INDEX_op_update_neg_cc] = CC_OSZAPC,
3826        /* subtle: due to the incl/decl implementation, C is used */
3827        [INDEX_op_update_inc_cc] = CC_OSZAPC,
3828        [INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
3829    
3830      [INDEX_op_adcb_T0_T1_cc] = CC_OSZAPC,      [INDEX_op_adcb_T0_T1_cc] = CC_OSZAPC,
3831      [INDEX_op_adcw_T0_T1_cc] = CC_OSZAPC,      [INDEX_op_adcw_T0_T1_cc] = CC_OSZAPC,
3832      [INDEX_op_adcl_T0_T1_cc] = CC_OSZAPC,      [INDEX_op_adcl_T0_T1_cc] = CC_OSZAPC,
3833      [INDEX_op_sbbb_T0_T1_cc] = CC_OSZAPC,      [INDEX_op_sbbb_T0_T1_cc] = CC_OSZAPC,
3834      [INDEX_op_sbbw_T0_T1_cc] = CC_OSZAPC,      [INDEX_op_sbbw_T0_T1_cc] = CC_OSZAPC,
3835      [INDEX_op_sbbl_T0_T1_cc] = CC_OSZAPC,      [INDEX_op_sbbl_T0_T1_cc] = CC_OSZAPC,
3836      [INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,  
3837      [INDEX_op_update_neg_cc] = CC_OSZAPC,      [INDEX_op_adcb_mem_T0_T1_cc] = CC_OSZAPC,
3838      /* subtle: due to the incl/decl implementation, C is used */      [INDEX_op_adcw_mem_T0_T1_cc] = CC_OSZAPC,
3839      [INDEX_op_update_inc_cc] = CC_OSZAPC,      [INDEX_op_adcl_mem_T0_T1_cc] = CC_OSZAPC,
3840      [INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,      [INDEX_op_sbbb_mem_T0_T1_cc] = CC_OSZAPC,
3841        [INDEX_op_sbbw_mem_T0_T1_cc] = CC_OSZAPC,
3842        [INDEX_op_sbbl_mem_T0_T1_cc] = CC_OSZAPC,
3843    
3844      [INDEX_op_mulb_AL_T0] = CC_OSZAPC,      [INDEX_op_mulb_AL_T0] = CC_OSZAPC,
3845      [INDEX_op_imulb_AL_T0] = CC_OSZAPC,      [INDEX_op_imulb_AL_T0] = CC_OSZAPC,
# Line 3795  static uint16_t opc_write_flags[NB_OPS] Line 3901  static uint16_t opc_write_flags[NB_OPS]
3901      [INDEX_op_shrdw_T0_T1_im_cc] = CC_OSZAPC,      [INDEX_op_shrdw_T0_T1_im_cc] = CC_OSZAPC,
3902      [INDEX_op_shrdl_T0_T1_im_cc] = CC_OSZAPC,      [INDEX_op_shrdl_T0_T1_im_cc] = CC_OSZAPC,
3903    
3904        [INDEX_op_rolb_mem_T0_T1_cc] = CC_O | CC_C,
3905        [INDEX_op_rolw_mem_T0_T1_cc] = CC_O | CC_C,
3906        [INDEX_op_roll_mem_T0_T1_cc] = CC_O | CC_C,
3907        [INDEX_op_rorb_mem_T0_T1_cc] = CC_O | CC_C,
3908        [INDEX_op_rorw_mem_T0_T1_cc] = CC_O | CC_C,
3909        [INDEX_op_rorl_mem_T0_T1_cc] = CC_O | CC_C,
3910    
3911        [INDEX_op_rclb_mem_T0_T1_cc] = CC_O | CC_C,
3912        [INDEX_op_rclw_mem_T0_T1_cc] = CC_O | CC_C,
3913        [INDEX_op_rcll_mem_T0_T1_cc] = CC_O | CC_C,
3914        [INDEX_op_rcrb_mem_T0_T1_cc] = CC_O | CC_C,
3915        [INDEX_op_rcrw_mem_T0_T1_cc] = CC_O | CC_C,
3916        [INDEX_op_rcrl_mem_T0_T1_cc] = CC_O | CC_C,
3917    
3918        [INDEX_op_shlb_mem_T0_T1_cc] = CC_OSZAPC,
3919        [INDEX_op_shlw_mem_T0_T1_cc] = CC_OSZAPC,
3920        [INDEX_op_shll_mem_T0_T1_cc] = CC_OSZAPC,
3921    
3922        [INDEX_op_shrb_mem_T0_T1_cc] = CC_OSZAPC,
3923        [INDEX_op_shrw_mem_T0_T1_cc] = CC_OSZAPC,
3924        [INDEX_op_shrl_mem_T0_T1_cc] = CC_OSZAPC,
3925    
3926        [INDEX_op_sarb_mem_T0_T1_cc] = CC_OSZAPC,
3927        [INDEX_op_sarw_mem_T0_T1_cc] = CC_OSZAPC,
3928        [INDEX_op_sarl_mem_T0_T1_cc] = CC_OSZAPC,
3929    
3930        [INDEX_op_shldw_mem_T0_T1_ECX_cc] = CC_OSZAPC,
3931        [INDEX_op_shldl_mem_T0_T1_ECX_cc] = CC_OSZAPC,
3932        [INDEX_op_shldw_mem_T0_T1_im_cc] = CC_OSZAPC,
3933        [INDEX_op_shldl_mem_T0_T1_im_cc] = CC_OSZAPC,
3934    
3935        [INDEX_op_shrdw_mem_T0_T1_ECX_cc] = CC_OSZAPC,
3936        [INDEX_op_shrdl_mem_T0_T1_ECX_cc] = CC_OSZAPC,
3937        [INDEX_op_shrdw_mem_T0_T1_im_cc] = CC_OSZAPC,
3938        [INDEX_op_shrdl_mem_T0_T1_im_cc] = CC_OSZAPC,
3939    
3940      [INDEX_op_btw_T0_T1_cc] = CC_OSZAPC,      [INDEX_op_btw_T0_T1_cc] = CC_OSZAPC,
3941      [INDEX_op_btl_T0_T1_cc] = CC_OSZAPC,      [INDEX_op_btl_T0_T1_cc] = CC_OSZAPC,
3942      [INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC,      [INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC,
# Line 3832  static uint16_t opc_write_flags[NB_OPS] Line 3974  static uint16_t opc_write_flags[NB_OPS]
3974      [INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC,      [INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC,
3975      [INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,      [INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
3976    
3977        [INDEX_op_cmpxchgb_mem_T0_T1_EAX_cc] = CC_OSZAPC,
3978        [INDEX_op_cmpxchgw_mem_T0_T1_EAX_cc] = CC_OSZAPC,
3979        [INDEX_op_cmpxchgl_mem_T0_T1_EAX_cc] = CC_OSZAPC,
3980    
3981      [INDEX_op_cmpxchg8b] = CC_Z,      [INDEX_op_cmpxchg8b] = CC_Z,
3982      [INDEX_op_lar] = CC_Z,      [INDEX_op_lar] = CC_Z,
3983      [INDEX_op_lsl] = CC_Z,      [INDEX_op_lsl] = CC_Z,
# Line 3844  static uint16_t opc_simpler[NB_OPS] = { Line 3990  static uint16_t opc_simpler[NB_OPS] = {
3990      [INDEX_op_update2_cc] = INDEX_op_nop,      [INDEX_op_update2_cc] = INDEX_op_nop,
3991      [INDEX_op_update1_cc] = INDEX_op_nop,      [INDEX_op_update1_cc] = INDEX_op_nop,
3992      [INDEX_op_update_neg_cc] = INDEX_op_nop,      [INDEX_op_update_neg_cc] = INDEX_op_nop,
3993    #if 0
3994        /* broken: CC_OP logic must be rewritten */
3995      [INDEX_op_update_inc_cc] = INDEX_op_nop,      [INDEX_op_update_inc_cc] = INDEX_op_nop,
3996    #endif
3997      [INDEX_op_rolb_T0_T1_cc] = INDEX_op_rolb_T0_T1,      [INDEX_op_rolb_T0_T1_cc] = INDEX_op_rolb_T0_T1,
3998      [INDEX_op_rolw_T0_T1_cc] = INDEX_op_rolw_T0_T1,      [INDEX_op_rolw_T0_T1_cc] = INDEX_op_rolw_T0_T1,
3999      [INDEX_op_roll_T0_T1_cc] = INDEX_op_roll_T0_T1,      [INDEX_op_roll_T0_T1_cc] = INDEX_op_roll_T0_T1,
# Line 3854  static uint16_t opc_simpler[NB_OPS] = { Line 4002  static uint16_t opc_simpler[NB_OPS] = {
4002      [INDEX_op_rorw_T0_T1_cc] = INDEX_op_rorw_T0_T1,      [INDEX_op_rorw_T0_T1_cc] = INDEX_op_rorw_T0_T1,
4003      [INDEX_op_rorl_T0_T1_cc] = INDEX_op_rorl_T0_T1,      [INDEX_op_rorl_T0_T1_cc] = INDEX_op_rorl_T0_T1,
4004    
4005        [INDEX_op_rolb_mem_T0_T1_cc] = INDEX_op_rolb_mem_T0_T1,
4006        [INDEX_op_rolw_mem_T0_T1_cc] = INDEX_op_rolw_mem_T0_T1,
4007        [INDEX_op_roll_mem_T0_T1_cc] = INDEX_op_roll_mem_T0_T1,
4008    
4009        [INDEX_op_rorb_mem_T0_T1_cc] = INDEX_op_rorb_mem_T0_T1,
4010        [INDEX_op_rorw_mem_T0_T1_cc] = INDEX_op_rorw_mem_T0_T1,
4011        [INDEX_op_rorl_mem_T0_T1_cc] = INDEX_op_rorl_mem_T0_T1,
4012    
4013      [INDEX_op_shlb_T0_T1_cc] = INDEX_op_shlb_T0_T1,      [INDEX_op_shlb_T0_T1_cc] = INDEX_op_shlb_T0_T1,
4014      [INDEX_op_shlw_T0_T1_cc] = INDEX_op_shlw_T0_T1,      [INDEX_op_shlw_T0_T1_cc] = INDEX_op_shlw_T0_T1,
4015      [INDEX_op_shll_T0_T1_cc] = INDEX_op_shll_T0_T1,      [INDEX_op_shll_T0_T1_cc] = INDEX_op_shll_T0_T1,
# Line 3971  static inline int gen_intermediate_code_ Line 4127  static inline int gen_intermediate_code_
4127              break;              break;
4128      } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&      } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
4129               (pc_ptr - pc_start) < (TARGET_PAGE_SIZE - 32));               (pc_ptr - pc_start) < (TARGET_PAGE_SIZE - 32));
4130        if (!dc->tf && dc->is_jmp == DISAS_NEXT) {
4131            gen_jmp(dc, ret - (unsigned long)dc->cs_base);
4132        }
4133    
4134      /* we must store the eflags state if it is not already done */      /* we must store the eflags state if it is not already done */
4135      if (dc->is_jmp != DISAS_TB_JUMP) {      if (dc->is_jmp != DISAS_TB_JUMP) {
4136          if (dc->cc_op != CC_OP_DYNAMIC)          if (dc->cc_op != CC_OP_DYNAMIC)
# Line 3983  static inline int gen_intermediate_code_ Line 4143  static inline int gen_intermediate_code_
4143      if (dc->tf) {      if (dc->tf) {
4144          gen_op_raise_exception(EXCP01_SSTP);          gen_op_raise_exception(EXCP01_SSTP);
4145      }      }
4146      if (dc->is_jmp != 3) {      if (dc->is_jmp != DISAS_TB_JUMP) {
4147          /* indicate that the hash table must be used to find the next TB */          /* indicate that the hash table must be used to find the next TB */
4148          gen_op_movl_T0_0();          gen_op_movl_T0_0();
4149      }      }
4150      *gen_opc_ptr = INDEX_op_end;      *gen_opc_ptr = INDEX_op_end;
4151        /* we don't forget to fill the last values */
4152        if (search_pc) {
4153            j = gen_opc_ptr - gen_opc_buf;
4154            lj++;
4155            while (lj <= j)
4156                gen_opc_instr_start[lj++] = 0;
4157        }
4158            
4159  #ifdef DEBUG_DISAS  #ifdef DEBUG_DISAS
4160      if (loglevel) {      if (loglevel) {
4161          fprintf(logfile, "----------------\n");          fprintf(logfile, "----------------\n");

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