1395 |
if (!supervisor(dc)) |
if (!supervisor(dc)) |
1396 |
goto priv_insn; |
goto priv_insn; |
1397 |
gen_op_sta(insn, 0, 4, 0); |
gen_op_sta(insn, 0, 4, 0); |
1398 |
break; |
break; |
1399 |
case 0x15: |
case 0x15: |
1400 |
if (!supervisor(dc)) |
if (!supervisor(dc)) |
1401 |
goto priv_insn; |
goto priv_insn; |
1402 |
gen_op_stba(insn, 0, 1, 0); |
gen_op_stba(insn, 0, 1, 0); |
1403 |
break; |
break; |
1404 |
case 0x16: |
case 0x16: |
1405 |
if (!supervisor(dc)) |
if (!supervisor(dc)) |
1406 |
goto priv_insn; |
goto priv_insn; |
1407 |
gen_op_stha(insn, 0, 2, 0); |
gen_op_stha(insn, 0, 2, 0); |
1408 |
break; |
break; |
1409 |
case 0x17: |
case 0x17: |
1410 |
if (!supervisor(dc)) |
if (!supervisor(dc)) |
1411 |
goto priv_insn; |
goto priv_insn; |
1412 |
flush_T2(dc); |
flush_T2(dc); |
1413 |
gen_movl_reg_T2(rd + 1); |
gen_movl_reg_T2(rd + 1); |
1414 |
gen_op_stda(insn, 0, 8, 0); |
gen_op_stda(insn, 0, 8, 0); |
1415 |
break; |
break; |
1416 |
#endif |
#endif |
1417 |
default: |
default: |
1418 |
case 0x0e: /* V9 stx */ |
case 0x0e: /* V9 stx */ |
1545 |
/* if the next PC is different, we abort now */ |
/* if the next PC is different, we abort now */ |
1546 |
if (dc->pc != (last_pc + 4)) |
if (dc->pc != (last_pc + 4)) |
1547 |
break; |
break; |
1548 |
|
/* if we reach a page boundary, we stop generation so that the |
1549 |
|
PC of a TT_TFAULT exception is always in the right page */ |
1550 |
|
if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) |
1551 |
|
break; |
1552 |
/* if single step mode, we generate only one instruction and |
/* if single step mode, we generate only one instruction and |
1553 |
generate an exception */ |
generate an exception */ |
1554 |
if (env->singlestep_enabled) { |
if (env->singlestep_enabled) { |