105 |
int reg = (T0 >> 8) & 0xf; |
int reg = (T0 >> 8) & 0xf; |
106 |
|
|
107 |
ret = env->mmuregs[reg]; |
ret = env->mmuregs[reg]; |
108 |
if (reg == 3 || reg == 4) /* Fault status, addr cleared on read*/ |
if (reg == 3) /* Fault status cleared on read */ |
109 |
env->mmuregs[4] = 0; |
env->mmuregs[reg] = 0; |
110 |
|
#ifdef DEBUG_MMU |
111 |
|
printf("mmu_read: reg[%d] = 0x%08x\n", reg, ret); |
112 |
|
#endif |
113 |
} |
} |
114 |
break; |
break; |
115 |
case 0x20 ... 0x2f: /* MMU passthrough */ |
case 0x20 ... 0x2f: /* MMU passthrough */ |
134 |
int mmulev; |
int mmulev; |
135 |
|
|
136 |
mmulev = (T0 >> 8) & 15; |
mmulev = (T0 >> 8) & 15; |
137 |
|
#ifdef DEBUG_MMU |
138 |
|
printf("mmu flush level %d\n", mmulev); |
139 |
|
#endif |
140 |
switch (mmulev) { |
switch (mmulev) { |
141 |
case 0: // flush page |
case 0: // flush page |
142 |
tlb_flush_page(cpu_single_env, T0 & 0xfffff000); |
tlb_flush_page(env, T0 & 0xfffff000); |
143 |
break; |
break; |
144 |
case 1: // flush segment (256k) |
case 1: // flush segment (256k) |
145 |
case 2: // flush region (16M) |
case 2: // flush region (16M) |
146 |
case 3: // flush context (4G) |
case 3: // flush context (4G) |
147 |
case 4: // flush entire |
case 4: // flush entire |
148 |
tlb_flush(cpu_single_env, 1); |
tlb_flush(env, 1); |
149 |
break; |
break; |
150 |
default: |
default: |
151 |
break; |
break; |
152 |
} |
} |
153 |
|
#ifdef DEBUG_MMU |
154 |
dump_mmu(); |
dump_mmu(); |
155 |
|
#endif |
156 |
return; |
return; |
157 |
} |
} |
158 |
case 4: /* write MMU regs */ |
case 4: /* write MMU regs */ |
160 |
int reg = (T0 >> 8) & 0xf, oldreg; |
int reg = (T0 >> 8) & 0xf, oldreg; |
161 |
|
|
162 |
oldreg = env->mmuregs[reg]; |
oldreg = env->mmuregs[reg]; |
163 |
if (reg == 0) { |
switch(reg) { |
164 |
|
case 0: |
165 |
env->mmuregs[reg] &= ~(MMU_E | MMU_NF); |
env->mmuregs[reg] &= ~(MMU_E | MMU_NF); |
166 |
env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF); |
env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF); |
167 |
} else |
if ((oldreg & MMU_E) != (env->mmuregs[reg] & MMU_E)) |
168 |
|
tlb_flush(env, 1); |
169 |
|
break; |
170 |
|
case 2: |
171 |
env->mmuregs[reg] = T1; |
env->mmuregs[reg] = T1; |
172 |
if (oldreg != env->mmuregs[reg]) { |
if (oldreg != env->mmuregs[reg]) { |
173 |
#if 0 |
/* we flush when the MMU context changes because |
174 |
// XXX: Only if MMU mapping change, we may need to flush? |
QEMU has no MMU context support */ |
175 |
tlb_flush(cpu_single_env, 1); |
tlb_flush(env, 1); |
176 |
cpu_loop_exit(); |
} |
177 |
FORCE_RET(); |
break; |
178 |
#endif |
case 3: |
179 |
} |
case 4: |
180 |
|
break; |
181 |
|
default: |
182 |
|
env->mmuregs[reg] = T1; |
183 |
|
break; |
184 |
|
} |
185 |
|
#ifdef DEBUG_MMU |
186 |
|
if (oldreg != env->mmuregs[reg]) { |
187 |
|
printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]); |
188 |
|
} |
189 |
dump_mmu(); |
dump_mmu(); |
190 |
|
#endif |
191 |
return; |
return; |
192 |
} |
} |
193 |
case 0x17: /* Block copy, sta access */ |
case 0x17: /* Block copy, sta access */ |