138 |
} |
} |
139 |
|
|
140 |
*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1); |
*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1); |
141 |
|
*physical = 0xfffff000; |
142 |
|
|
143 |
/* SPARC reference MMU table walk: Context table->L1->L2->PTE */ |
/* SPARC reference MMU table walk: Context table->L1->L2->PTE */ |
144 |
/* Context base + context number */ |
/* Context base + context number */ |
211 |
/* check access */ |
/* check access */ |
212 |
access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; |
access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; |
213 |
error_code = access_table[*access_index][access_perms]; |
error_code = access_table[*access_index][access_perms]; |
214 |
if (error_code) |
if (error_code && !(env->mmuregs[0] & MMU_NF)) |
215 |
return error_code; |
return error_code; |
216 |
|
|
217 |
/* the page can be put in the TLB */ |
/* the page can be put in the TLB */ |
226 |
/* Even if large ptes, we map only one 4KB page in the cache to |
/* Even if large ptes, we map only one 4KB page in the cache to |
227 |
avoid filling it too fast */ |
avoid filling it too fast */ |
228 |
*physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset; |
*physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset; |
229 |
return 0; |
return error_code; |
230 |
} |
} |
231 |
|
|
232 |
/* Perform address translation */ |
/* Perform address translation */ |
252 |
env->mmuregs[4] = address; /* Fault address register */ |
env->mmuregs[4] = address; /* Fault address register */ |
253 |
|
|
254 |
if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { |
if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { |
255 |
#if 0 |
// No fault mode: if a mapping is available, just override |
256 |
// No fault |
// permissions. If no mapping is available, redirect accesses to |
257 |
|
// neverland. Fake/overridden mappings will be flushed when |
258 |
|
// switching to normal mode. |
259 |
vaddr = address & TARGET_PAGE_MASK; |
vaddr = address & TARGET_PAGE_MASK; |
|
paddr = 0xfffff000; |
|
260 |
prot = PAGE_READ | PAGE_WRITE; |
prot = PAGE_READ | PAGE_WRITE; |
261 |
ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu); |
ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu); |
262 |
return ret; |
return ret; |
|
#else |
|
|
cpu_abort(env, "MMU no fault case no handled"); |
|
|
return 0; |
|
|
#endif |
|
263 |
} else { |
} else { |
264 |
if (rw & 2) |
if (rw & 2) |
265 |
env->exception_index = TT_TFAULT; |
env->exception_index = TT_TFAULT; |
314 |
count, intno, |
count, intno, |
315 |
env->pc, |
env->pc, |
316 |
env->npc, env->regwptr[6]); |
env->npc, env->regwptr[6]); |
|
#if 1 |
|
317 |
cpu_dump_state(env, logfile, fprintf, 0); |
cpu_dump_state(env, logfile, fprintf, 0); |
318 |
|
#if 0 |
319 |
{ |
{ |
320 |
int i; |
int i; |
321 |
uint8_t *ptr; |
uint8_t *ptr; |