18 |
/*#define EXCP_INTERRUPT 0x100*/ |
/*#define EXCP_INTERRUPT 0x100*/ |
19 |
|
|
20 |
/* trap definitions */ |
/* trap definitions */ |
21 |
|
#define TT_TFAULT 0x01 |
22 |
#define TT_ILL_INSN 0x02 |
#define TT_ILL_INSN 0x02 |
23 |
#define TT_PRIV_INSN 0x03 |
#define TT_PRIV_INSN 0x03 |
24 |
#define TT_NFPU_INSN 0x04 |
#define TT_NFPU_INSN 0x04 |
25 |
#define TT_WIN_OVF 0x05 |
#define TT_WIN_OVF 0x05 |
26 |
#define TT_WIN_UNF 0x06 |
#define TT_WIN_UNF 0x06 |
27 |
#define TT_FP_EXCP 0x08 |
#define TT_FP_EXCP 0x08 |
28 |
|
#define TT_DFAULT 0x09 |
29 |
|
#define TT_EXTINT 0x10 |
30 |
#define TT_DIV_ZERO 0x2a |
#define TT_DIV_ZERO 0x2a |
31 |
#define TT_TRAP 0x80 |
#define TT_TRAP 0x80 |
|
#define TT_EXTINT 0x10 |
|
32 |
|
|
33 |
#define PSR_NEG (1<<23) |
#define PSR_NEG (1<<23) |
34 |
#define PSR_ZERO (1<<22) |
#define PSR_ZERO (1<<22) |
144 |
/* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */ |
/* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */ |
145 |
CPUTLBEntry tlb_read[2][CPU_TLB_SIZE]; |
CPUTLBEntry tlb_read[2][CPU_TLB_SIZE]; |
146 |
CPUTLBEntry tlb_write[2][CPU_TLB_SIZE]; |
CPUTLBEntry tlb_write[2][CPU_TLB_SIZE]; |
|
int error_code; |
|
147 |
/* MMU regs */ |
/* MMU regs */ |
148 |
uint32_t mmuregs[16]; |
uint32_t mmuregs[16]; |
149 |
/* temporary float registers */ |
/* temporary float registers */ |