166 |
int exception_index; |
int exception_index; |
167 |
int interrupt_index; |
int interrupt_index; |
168 |
int interrupt_request; |
int interrupt_request; |
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struct TranslationBlock *current_tb; |
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|
void *opaque; |
|
169 |
/* NOTE: we allow 8 more registers to handle wrapping */ |
/* NOTE: we allow 8 more registers to handle wrapping */ |
170 |
target_ulong regbase[NWINDOWS * 16 + 8]; |
target_ulong regbase[NWINDOWS * 16 + 8]; |
171 |
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|
172 |
/* in order to avoid passing too many arguments to the memory |
CPU_COMMON |
173 |
write helpers, we store some rarely used information in the CPU |
|
|
context) */ |
|
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unsigned long mem_write_pc; /* host pc at which the memory was |
|
|
written */ |
|
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target_ulong mem_write_vaddr; /* target virtual addr at which the |
|
|
memory was written */ |
|
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/* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */ |
|
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CPUTLBEntry tlb_read[2][CPU_TLB_SIZE]; |
|
|
CPUTLBEntry tlb_write[2][CPU_TLB_SIZE]; |
|
174 |
/* MMU regs */ |
/* MMU regs */ |
175 |
#if defined(TARGET_SPARC64) |
#if defined(TARGET_SPARC64) |
176 |
uint64_t lsu; |
uint64_t lsu; |
212 |
#if !defined(TARGET_SPARC64) && !defined(reg_T2) |
#if !defined(TARGET_SPARC64) && !defined(reg_T2) |
213 |
target_ulong t2; |
target_ulong t2; |
214 |
#endif |
#endif |
|
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|
|
/* ice debug support */ |
|
|
target_ulong breakpoints[MAX_BREAKPOINTS]; |
|
|
int nb_breakpoints; |
|
|
int singlestep_enabled; /* XXX: should use CPU single step mode instead */ |
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|
|
|
215 |
} CPUSPARCState; |
} CPUSPARCState; |
216 |
#if defined(TARGET_SPARC64) |
#if defined(TARGET_SPARC64) |
217 |
#define GET_FSR32(env) (env->fsr & 0xcfc1ffff) |
#define GET_FSR32(env) (env->fsr & 0xcfc1ffff) |