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/* |
/* |
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* PPC emulation helpers for qemu. |
* PowerPC emulation helpers for qemu. |
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* |
* |
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* Copyright (c) 2003 Jocelyn Mayer |
* Copyright (c) 2003-2005 Jocelyn Mayer |
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* |
* |
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* This library is free software; you can redistribute it and/or |
* This library is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU Lesser General Public |
* modify it under the terms of the GNU Lesser General Public |
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/*****************************************************************************/ |
/*****************************************************************************/ |
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/* Helpers for "fat" micro operations */ |
/* Helpers for "fat" micro operations */ |
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/* Special registers load and store */ |
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void do_load_cr (void) |
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{ |
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T0 = (env->crf[0] << 28) | |
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(env->crf[1] << 24) | |
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(env->crf[2] << 20) | |
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(env->crf[3] << 16) | |
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(env->crf[4] << 12) | |
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(env->crf[5] << 8) | |
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(env->crf[6] << 4) | |
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(env->crf[7] << 0); |
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} |
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void do_store_cr (uint32_t mask) |
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{ |
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int i, sh; |
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for (i = 0, sh = 7; i < 8; i++, sh --) { |
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if (mask & (1 << sh)) |
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env->crf[i] = (T0 >> (sh * 4)) & 0xF; |
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} |
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} |
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void do_load_xer (void) |
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{ |
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T0 = (xer_so << XER_SO) | |
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(xer_ov << XER_OV) | |
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(xer_ca << XER_CA) | |
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(xer_bc << XER_BC); |
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} |
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void do_store_xer (void) |
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{ |
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xer_so = (T0 >> XER_SO) & 0x01; |
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xer_ov = (T0 >> XER_OV) & 0x01; |
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xer_ca = (T0 >> XER_CA) & 0x01; |
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xer_bc = (T0 >> XER_BC) & 0x3f; |
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} |
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void do_load_msr (void) |
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{ |
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T0 = (msr_pow << MSR_POW) | |
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(msr_ile << MSR_ILE) | |
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(msr_ee << MSR_EE) | |
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(msr_pr << MSR_PR) | |
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(msr_fp << MSR_FP) | |
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(msr_me << MSR_ME) | |
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(msr_fe0 << MSR_FE0) | |
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(msr_se << MSR_SE) | |
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(msr_be << MSR_BE) | |
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(msr_fe1 << MSR_FE1) | |
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(msr_ip << MSR_IP) | |
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(msr_ir << MSR_IR) | |
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(msr_dr << MSR_DR) | |
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(msr_ri << MSR_RI) | |
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(msr_le << MSR_LE); |
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} |
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void do_store_msr (void) |
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{ |
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#if 1 // TRY |
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if (((T0 >> MSR_IR) & 0x01) != msr_ir || |
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((T0 >> MSR_DR) & 0x01) != msr_dr || |
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((T0 >> MSR_PR) & 0x01) != msr_pr) |
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{ |
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do_tlbia(); |
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} |
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#endif |
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msr_pow = (T0 >> MSR_POW) & 0x03; |
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msr_ile = (T0 >> MSR_ILE) & 0x01; |
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msr_ee = (T0 >> MSR_EE) & 0x01; |
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msr_pr = (T0 >> MSR_PR) & 0x01; |
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msr_fp = (T0 >> MSR_FP) & 0x01; |
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msr_me = (T0 >> MSR_ME) & 0x01; |
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msr_fe0 = (T0 >> MSR_FE0) & 0x01; |
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msr_se = (T0 >> MSR_SE) & 0x01; |
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msr_be = (T0 >> MSR_BE) & 0x01; |
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msr_fe1 = (T0 >> MSR_FE1) & 0x01; |
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msr_ip = (T0 >> MSR_IP) & 0x01; |
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msr_ir = (T0 >> MSR_IR) & 0x01; |
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msr_dr = (T0 >> MSR_DR) & 0x01; |
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msr_ri = (T0 >> MSR_RI) & 0x01; |
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msr_le = (T0 >> MSR_LE) & 0x01; |
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} |
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/* shift right arithmetic helper */ |
/* shift right arithmetic helper */ |
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void do_sraw (void) |
void do_sraw (void) |
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{ |
{ |
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} |
} |
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/* Floating point operations helpers */ |
/* Floating point operations helpers */ |
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void do_load_fpscr (void) |
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{ |
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/* The 32 MSB of the target fpr are undefined. |
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* They'll be zero... |
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*/ |
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union { |
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double d; |
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struct { |
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uint32_t u[2]; |
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} s; |
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} u; |
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int i; |
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#ifdef WORDS_BIGENDIAN |
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#define WORD0 0 |
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#define WORD1 1 |
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#else |
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#define WORD0 1 |
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#define WORD1 0 |
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#endif |
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u.s.u[WORD0] = 0; |
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u.s.u[WORD1] = 0; |
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for (i = 0; i < 8; i++) |
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u.s.u[WORD1] |= env->fpscr[i] << (4 * i); |
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FT0 = u.d; |
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} |
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void do_store_fpscr (uint32_t mask) |
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{ |
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/* |
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* We use only the 32 LSB of the incoming fpr |
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*/ |
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union { |
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double d; |
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struct { |
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uint32_t u[2]; |
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} s; |
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} u; |
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int i, rnd_type; |
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u.d = FT0; |
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if (mask & 0x80) |
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env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9); |
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for (i = 1; i < 7; i++) { |
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if (mask & (1 << (7 - i))) |
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env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF; |
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} |
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/* TODO: update FEX & VX */ |
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/* Set rounding mode */ |
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switch (env->fpscr[0] & 0x3) { |
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case 0: |
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/* Best approximation (round to nearest) */ |
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rnd_type = float_round_nearest_even; |
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break; |
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case 1: |
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/* Smaller magnitude (round toward zero) */ |
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rnd_type = float_round_to_zero; |
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break; |
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case 2: |
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/* Round toward +infinite */ |
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rnd_type = float_round_up; |
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break; |
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default: |
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case 3: |
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/* Round toward -infinite */ |
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rnd_type = float_round_down; |
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break; |
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} |
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set_float_rounding_mode(rnd_type, &env->fp_status); |
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} |
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void do_fctiw (void) |
void do_fctiw (void) |
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{ |
{ |
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union { |
union { |
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} p; |
} p; |
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/* XXX: higher bits are not supposed to be significant. |
/* XXX: higher bits are not supposed to be significant. |
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* to make tests easier, return the same as a real PPC 750 (aka G3) |
* to make tests easier, return the same as a real PowerPC 750 (aka G3) |
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*/ |
*/ |
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p.i = float64_to_int32(FT0, &env->fp_status); |
p.i = float64_to_int32(FT0, &env->fp_status); |
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p.i |= 0xFFF80000ULL << 32; |
p.i |= 0xFFF80000ULL << 32; |
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} p; |
} p; |
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/* XXX: higher bits are not supposed to be significant. |
/* XXX: higher bits are not supposed to be significant. |
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* to make tests easier, return the same as a real PPC 750 (aka G3) |
* to make tests easier, return the same as a real PowerPC 750 (aka G3) |
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*/ |
*/ |
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p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status); |
p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status); |
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p.i |= 0xFFF80000ULL << 32; |
p.i |= 0xFFF80000ULL << 32; |
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tlb_flush_page(env, T0); |
tlb_flush_page(env, T0); |
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} |
} |
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void do_store_sr (uint32_t srnum) |
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{ |
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#if defined (DEBUG_OP) |
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dump_store_sr(srnum); |
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#endif |
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#if 0 // TRY |
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{ |
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uint32_t base, page; |
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base = srnum << 28; |
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for (page = base; page != base + 0x100000000; page += 0x1000) |
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tlb_flush_page(env, page); |
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} |
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#else |
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tlb_flush(env, 1); |
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#endif |
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env->sr[srnum] = T0; |
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} |
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/* For BATs, we may not invalidate any TLBs if the change is only on |
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* protection bits for user mode. |
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*/ |
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void do_store_ibat (int ul, int nr) |
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{ |
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#if defined (DEBUG_OP) |
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dump_store_ibat(ul, nr); |
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#endif |
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#if 0 // TRY |
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{ |
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uint32_t base, length, page; |
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base = env->IBAT[0][nr]; |
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length = (((base >> 2) & 0x000007FF) + 1) << 17; |
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base &= 0xFFFC0000; |
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for (page = base; page != base + length; page += 0x1000) |
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tlb_flush_page(env, page); |
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} |
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#else |
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tlb_flush(env, 1); |
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#endif |
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env->IBAT[ul][nr] = T0; |
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} |
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void do_store_dbat (int ul, int nr) |
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{ |
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#if defined (DEBUG_OP) |
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dump_store_dbat(ul, nr); |
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#endif |
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#if 0 // TRY |
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{ |
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uint32_t base, length, page; |
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base = env->DBAT[0][nr]; |
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length = (((base >> 2) & 0x000007FF) + 1) << 17; |
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base &= 0xFFFC0000; |
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for (page = base; page != base + length; page += 0x1000) |
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tlb_flush_page(env, page); |
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} |
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#else |
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tlb_flush(env, 1); |
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#endif |
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env->DBAT[ul][nr] = T0; |
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} |
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/*****************************************************************************/ |
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/* Special helpers for debug */ |
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void dump_state (void) |
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{ |
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// cpu_dump_state(env, stdout, fprintf, 0); |
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} |
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void dump_rfi (void) |
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{ |
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#if 0 |
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printf("Return from interrupt => 0x%08x\n", env->nip); |
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// cpu_dump_state(env, stdout, fprintf, 0); |
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#endif |
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} |
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void dump_store_sr (int srnum) |
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{ |
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#if 0 |
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printf("%s: reg=%d 0x%08x\n", __func__, srnum, T0); |
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#endif |
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} |
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static void _dump_store_bat (char ID, int ul, int nr) |
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{ |
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printf("Set %cBAT%d%c to 0x%08x (0x%08x)\n", |
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ID, nr, ul == 0 ? 'u' : 'l', T0, env->nip); |
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} |
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void dump_store_ibat (int ul, int nr) |
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{ |
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_dump_store_bat('I', ul, nr); |
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} |
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void dump_store_dbat (int ul, int nr) |
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{ |
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_dump_store_bat('D', ul, nr); |
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} |
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void dump_store_tb (int ul) |
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{ |
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printf("Set TB%c to 0x%08x\n", ul == 0 ? 'L' : 'U', T0); |
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} |
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void dump_update_tb(uint32_t param) |
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{ |
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#if 0 |
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printf("Update TB: 0x%08x + %d => 0x%08x\n", T1, param, T0); |
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#endif |
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} |
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