/[qemu]/qemu/target-ppc/cpu.h
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revision 1.21 by bellard, Mon Jul 4 22:17:05 2005 UTC revision 1.22 by bellard, Sun Nov 20 10:29:33 2005 UTC
# Line 493  struct CPUPPCState { Line 493  struct CPUPPCState {
493      /* floating point status and control register */      /* floating point status and control register */
494      uint8_t fpscr[8];      uint8_t fpscr[8];
495    
496      /* soft mmu support */      CPU_COMMON
497      /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */  
     CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];  
     CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];  
498      int access_type; /* when a memory exception occurs, the access      int access_type; /* when a memory exception occurs, the access
499                          type is stored here */                          type is stored here */
     /* in order to avoid passing too many arguments to the memory  
        write helpers, we store some rarely used information in the CPU  
        context) */  
     unsigned long mem_write_pc; /* host pc at which the memory was  
                                    written */  
     unsigned long mem_write_vaddr; /* target virtual addr at which the  
                                       memory was written */  
500    
501      /* MMU context */      /* MMU context */
502      /* Address space register */      /* Address space register */
# Line 564  struct CPUPPCState { Line 555  struct CPUPPCState {
555      /* Those resources are used only in Qemu core */      /* Those resources are used only in Qemu core */
556      jmp_buf jmp_env;      jmp_buf jmp_env;
557      int user_mode_only; /* user mode only simulation */      int user_mode_only; /* user mode only simulation */
     struct TranslationBlock *current_tb; /* currently executing TB */  
558      uint32_t hflags;      uint32_t hflags;
559    
     /* ice debug support */  
     target_ulong breakpoints[MAX_BREAKPOINTS];  
     int nb_breakpoints;  
     int singlestep_enabled; /* XXX: should use CPU single step mode instead */  
   
560      /* Power management */      /* Power management */
561      int power_mode;      int power_mode;
562    
563      /* temporary hack to handle OSI calls (only used if non NULL) */      /* temporary hack to handle OSI calls (only used if non NULL) */
564      int (*osi_call)(struct CPUPPCState *env);      int (*osi_call)(struct CPUPPCState *env);
   
     /* user data */  
     void *opaque;  
565  };  };
566    
567  /*****************************************************************************/  /*****************************************************************************/

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