/[qemu]/qemu/target-mips/translate.c
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Diff of /qemu/target-mips/translate.c

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revision 1.4 by bellard, Sat Jul 2 15:27:11 2005 UTC revision 1.5 by bellard, Sat Jul 2 15:28:16 2005 UTC
# Line 1454  void cpu_dump_state (CPUState *env, FILE Line 1454  void cpu_dump_state (CPUState *env, FILE
1454                       int (*cpu_fprintf)(FILE *f, const char *fmt, ...),                       int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1455                       int flags)                       int flags)
1456  {  {
1457        uint32_t c0_status;
1458      int i;      int i;
1459            
1460      cpu_fprintf(f, "pc=0x%08x HI=0x%08x LO=0x%08x ds %04x %08x %d\n",      cpu_fprintf(f, "pc=0x%08x HI=0x%08x LO=0x%08x ds %04x %08x %d\n",
# Line 1465  void cpu_dump_state (CPUState *env, FILE Line 1466  void cpu_dump_state (CPUState *env, FILE
1466          if ((i & 3) == 3)          if ((i & 3) == 3)
1467              cpu_fprintf(f, "\n");              cpu_fprintf(f, "\n");
1468      }      }
1469    
1470        c0_status = env->CP0_Status;
1471        if (env->hflags & MIPS_HFLAG_UM)
1472            c0_status |= (1 << CP0St_UM);
1473        if (env->hflags & MIPS_HFLAG_ERL)
1474            c0_status |= (1 << CP0St_ERL);
1475        if (env->hflags & MIPS_HFLAG_EXL)
1476            c0_status |= (1 << CP0St_EXL);
1477    
1478      cpu_fprintf(f, "CP0 Status  0x%08x Cause   0x%08x EPC    0x%08x\n",      cpu_fprintf(f, "CP0 Status  0x%08x Cause   0x%08x EPC    0x%08x\n",
1479                  env->CP0_Status, env->CP0_Cause, env->CP0_EPC);                  c0_status, env->CP0_Cause, env->CP0_EPC);
1480      cpu_fprintf(f, "    Config0 0x%08x Config1 0x%08x LLAddr 0x%08x\n",      cpu_fprintf(f, "    Config0 0x%08x Config1 0x%08x LLAddr 0x%08x\n",
1481                  env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);                  env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
1482  }  }

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