/[qemu]/qemu/target-mips/helper.c
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Diff of /qemu/target-mips/helper.c

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revision 1.7 by bellard, Mon Jul 4 22:17:32 2005 UTC revision 1.8 by bellard, Mon Dec 5 19:59:36 2005 UTC
# Line 46  static int map_address (CPUState *env, t Line 46  static int map_address (CPUState *env, t
46          tlb = &env->tlb[i];          tlb = &env->tlb[i];
47          /* Check ASID, virtual page number & size */          /* Check ASID, virtual page number & size */
48          if ((tlb->G == 1 || tlb->ASID == ASID) &&          if ((tlb->G == 1 || tlb->ASID == ASID) &&
49              tlb->VPN == tag && address < tlb->end) {              tlb->VPN == tag && address < tlb->end2) {
50              /* TLB match */              /* TLB match */
51              n = (address >> 12) & 1;              n = (address >> 12) & 1;
52              /* Check access rights */              /* Check access rights */
# Line 167  int cpu_mips_handle_mmu_fault (CPUState Line 167  int cpu_mips_handle_mmu_fault (CPUState
167      int ret = 0;      int ret = 0;
168    
169      if (logfile) {      if (logfile) {
170    #if 0
171          cpu_dump_state(env, logfile, fprintf, 0);          cpu_dump_state(env, logfile, fprintf, 0);
172    #endif
173          fprintf(logfile, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n",          fprintf(logfile, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n",
174                  __func__, env->PC, address, rw, is_user, is_softmmu);                  __func__, env->PC, address, rw, is_user, is_softmmu);
175      }      }
176    
177        rw &= 1;
178    
179      /* data access */      /* data access */
180      /* XXX: put correct access by using cpu_restore_state()      /* XXX: put correct access by using cpu_restore_state()
181         correctly */         correctly */
# Line 226  int cpu_mips_handle_mmu_fault (CPUState Line 231  int cpu_mips_handle_mmu_fault (CPUState
231          /* Raise exception */          /* Raise exception */
232          env->CP0_BadVAddr = address;          env->CP0_BadVAddr = address;
233          env->CP0_Context = (env->CP0_Context & 0xff800000) |          env->CP0_Context = (env->CP0_Context & 0xff800000) |
234                             ((address >> 8) &   0x007ffff0);                             ((address >> 9) &   0x007ffff0);
235          env->CP0_EntryHi =          env->CP0_EntryHi =
236              (env->CP0_EntryHi & 0x000000FF) | (address & 0xFFFFF000);              (env->CP0_EntryHi & 0x000000FF) | (address & 0xFFFFF000);
237          env->exception_index = exception;          env->exception_index = exception;
# Line 276  void do_interrupt (CPUState *env) Line 281  void do_interrupt (CPUState *env)
281          env->CP0_Debug |= 1 << CP0DB_DDBL;          env->CP0_Debug |= 1 << CP0DB_DDBL;
282          goto set_DEPC;          goto set_DEPC;
283      set_DEPC:      set_DEPC:
284          if (env->hflags & MIPS_HFLAG_DS) {          if (env->hflags & MIPS_HFLAG_BMASK) {
285              /* If the exception was raised from a delay slot,              /* If the exception was raised from a delay slot,
286               * come back to the jump               * come back to the jump
287               */               */
288              env->CP0_DEPC = env->PC - 4;              env->CP0_DEPC = env->PC - 4;
289                env->hflags &= ~MIPS_HFLAG_BMASK;
290          } else {          } else {
291              env->CP0_DEPC = env->PC;              env->CP0_DEPC = env->PC;
292          }          }
# Line 316  void do_interrupt (CPUState *env) Line 322  void do_interrupt (CPUState *env)
322          env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |          env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |
323              (1 << CP0St_NMI);              (1 << CP0St_NMI);
324      set_error_EPC:      set_error_EPC:
325          env->hflags = MIPS_HFLAG_ERL;          if (env->hflags & MIPS_HFLAG_BMASK) {
         if (env->hflags & MIPS_HFLAG_DS) {  
326              /* If the exception was raised from a delay slot,              /* If the exception was raised from a delay slot,
327               * come back to the jump               * come back to the jump
328               */               */
# Line 325  void do_interrupt (CPUState *env) Line 330  void do_interrupt (CPUState *env)
330          } else {          } else {
331              env->CP0_ErrorEPC = env->PC;              env->CP0_ErrorEPC = env->PC;
332          }          }
333            env->hflags = MIPS_HFLAG_ERL;
334          pc = 0xBFC00000;          pc = 0xBFC00000;
335          break;          break;
336      case EXCP_MCHECK:      case EXCP_MCHECK:
# Line 366  void do_interrupt (CPUState *env) Line 372  void do_interrupt (CPUState *env)
372          goto set_EPC;          goto set_EPC;
373      case EXCP_CpU:      case EXCP_CpU:
374          cause = 11;          cause = 11;
375          /* XXX: fill in the faulty unit number */          env->CP0_Cause = (env->CP0_Cause & ~0x03000000) | (env->error_code << 28);
376          goto set_EPC;          goto set_EPC;
377      case EXCP_OVERFLOW:      case EXCP_OVERFLOW:
378          cause = 12;          cause = 12;
# Line 391  void do_interrupt (CPUState *env) Line 397  void do_interrupt (CPUState *env)
397          env->hflags |= MIPS_HFLAG_EXL;          env->hflags |= MIPS_HFLAG_EXL;
398          pc += offset;          pc += offset;
399          env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);          env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
400          if (env->hflags & MIPS_HFLAG_DS) {          if (env->hflags & MIPS_HFLAG_BMASK) {
401              /* If the exception was raised from a delay slot,              /* If the exception was raised from a delay slot,
402               * come back to the jump               * come back to the jump
403               */               */
404              env->CP0_EPC = env->PC - 4;              env->CP0_EPC = env->PC - 4;
405              env->CP0_Cause |= 0x80000000;              env->CP0_Cause |= 0x80000000;
406                env->hflags &= ~MIPS_HFLAG_BMASK;
407          } else {          } else {
408              env->CP0_EPC = env->PC;              env->CP0_EPC = env->PC;
409              env->CP0_Cause &= ~0x80000000;              env->CP0_Cause &= ~0x80000000;

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