/[qemu]/qemu/target-mips/cpu.h
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revision 1.3 by bellard, Sun Nov 20 10:29:33 2005 UTC revision 1.4 by bellard, Mon Dec 5 19:59:36 2005 UTC
# Line 1  Line 1 
1  #if !defined (__MIPS_CPU_H__)  #if !defined (__MIPS_CPU_H__)
2  #define __MIPS_CPU_H__  #define __MIPS_CPU_H__
3    
4    #define TARGET_HAS_ICE 1
5    
6  #include "mips-defs.h"  #include "mips-defs.h"
7  #include "cpu-defs.h"  #include "cpu-defs.h"
8  #include "config.h"  #include "config.h"
# Line 18  typedef struct tlb_t tlb_t; Line 20  typedef struct tlb_t tlb_t;
20  struct tlb_t {  struct tlb_t {
21      target_ulong VPN;      target_ulong VPN;
22      target_ulong end;      target_ulong end;
23        target_ulong end2;
24      uint8_t ASID;      uint8_t ASID;
25      uint8_t G;      uint8_t G;
26      uint8_t C[2];      uint8_t C[2];
# Line 151  struct CPUMIPSState { Line 154  struct CPUMIPSState {
154  #define MIPS_HFLAG_DM     0x0008 /* Debug mode                         */  #define MIPS_HFLAG_DM     0x0008 /* Debug mode                         */
155  #define MIPS_HFLAG_SM     0x0010 /* Supervisor mode                    */  #define MIPS_HFLAG_SM     0x0010 /* Supervisor mode                    */
156  #define MIPS_HFLAG_RE     0x0040 /* Reversed endianness                */  #define MIPS_HFLAG_RE     0x0040 /* Reversed endianness                */
157  #define MIPS_HFLAG_DS     0x0080 /* In / out of delay slot             */      /* If translation is interrupted between the branch instruction and
158      /* Those flags keep the branch state if the translation is interrupted       * the delay slot, record what type of branch it is so that we can
159       * between the branch instruction and the delay slot       * resume translation properly.  It might be possible to reduce
160       */       * this from three bits to two.  */
161  #define MIPS_HFLAG_BMASK  0x0F00  #define MIPS_HFLAG_BMASK  0x0380
162  #define MIPS_HFLAG_B      0x0100 /* Unconditional branch               */  #define MIPS_HFLAG_B      0x0080 /* Unconditional branch               */
163  #define MIPS_HFLAG_BC     0x0200 /* Conditional branch                 */  #define MIPS_HFLAG_BC     0x0100 /* Conditional branch                 */
164  #define MIPS_HFLAG_BL     0x0400 /* Likely branch                      */  #define MIPS_HFLAG_BL     0x0180 /* Likely branch                      */
165  #define MIPS_HFLAG_BR     0x0800 /* branch to register (can't link TB) */  #define MIPS_HFLAG_BR     0x0200 /* branch to register (can't link TB) */
166      target_ulong btarget;        /* Jump / branch target               */      target_ulong btarget;        /* Jump / branch target               */
167      int bcond;                   /* Branch condition (if needed)       */      int bcond;                   /* Branch condition (if needed)       */
168    
169        int halted; /* TRUE if the CPU is in suspend state */
170    
171      CPU_COMMON      CPU_COMMON
172  };  };
173    
# Line 202  enum { Line 207  enum {
207      EXCP_IBE,      EXCP_IBE,
208      EXCP_DBp,      EXCP_DBp,
209      EXCP_SYSCALL,      EXCP_SYSCALL,
210      EXCP_BREAK,      EXCP_BREAK, /* 16 */
211      EXCP_CpU, /* 16 */      EXCP_CpU,
212      EXCP_RI,      EXCP_RI,
213      EXCP_OVERFLOW,      EXCP_OVERFLOW,
214      EXCP_TRAP,      EXCP_TRAP,
215      EXCP_DDBS,      EXCP_DDBS,
216      EXCP_DWATCH,      EXCP_DWATCH,
217      EXCP_LAE, /* 22 */      EXCP_LAE,
218      EXCP_SAE,      EXCP_SAE, /* 24 */
219      EXCP_LTLBL,      EXCP_LTLBL,
220      EXCP_TLBL,      EXCP_TLBL,
221      EXCP_TLBS,      EXCP_TLBS,

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