240 |
EXCP_FLUSH = 0x109, |
EXCP_FLUSH = 0x109, |
241 |
}; |
}; |
242 |
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/* MIPS opcodes */ |
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#define EXT_SPECIAL 0x100 |
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#define EXT_SPECIAL2 0x200 |
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#define EXT_REGIMM 0x300 |
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#define EXT_CP0 0x400 |
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#define EXT_CP1 0x500 |
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#define EXT_CP2 0x600 |
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#define EXT_CP3 0x700 |
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enum { |
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/* indirect opcode tables */ |
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OPC_SPECIAL = 0x00, |
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OPC_BREGIMM = 0x01, |
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OPC_CP0 = 0x10, |
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OPC_CP1 = 0x11, |
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OPC_CP2 = 0x12, |
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OPC_CP3 = 0x13, |
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OPC_SPECIAL2 = 0x1C, |
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/* arithmetic with immediate */ |
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OPC_ADDI = 0x08, |
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OPC_ADDIU = 0x09, |
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OPC_SLTI = 0x0A, |
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OPC_SLTIU = 0x0B, |
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OPC_ANDI = 0x0C, |
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OPC_ORI = 0x0D, |
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OPC_XORI = 0x0E, |
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OPC_LUI = 0x0F, |
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/* Jump and branches */ |
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OPC_J = 0x02, |
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OPC_JAL = 0x03, |
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OPC_BEQ = 0x04, /* Unconditional if rs = rt = 0 (B) */ |
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OPC_BEQL = 0x14, |
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OPC_BNE = 0x05, |
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OPC_BNEL = 0x15, |
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OPC_BLEZ = 0x06, |
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OPC_BLEZL = 0x16, |
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OPC_BGTZ = 0x07, |
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OPC_BGTZL = 0x17, |
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OPC_JALX = 0x1D, /* MIPS 16 only */ |
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/* Load and stores */ |
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OPC_LB = 0x20, |
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OPC_LH = 0x21, |
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OPC_LWL = 0x22, |
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OPC_LW = 0x23, |
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OPC_LBU = 0x24, |
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OPC_LHU = 0x25, |
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OPC_LWR = 0x26, |
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OPC_SB = 0x28, |
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OPC_SH = 0x29, |
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OPC_SWL = 0x2A, |
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OPC_SW = 0x2B, |
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OPC_SWR = 0x2E, |
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OPC_LL = 0x30, |
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OPC_SC = 0x38, |
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/* Floating point load/store */ |
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OPC_LWC1 = 0x31, |
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OPC_LWC2 = 0x32, |
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OPC_LDC1 = 0x35, |
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OPC_LDC2 = 0x36, |
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OPC_SWC1 = 0x39, |
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OPC_SWC2 = 0x3A, |
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OPC_SDC1 = 0x3D, |
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OPC_SDC2 = 0x3E, |
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/* Cache and prefetch */ |
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OPC_CACHE = 0x2F, |
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OPC_PREF = 0x33, |
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}; |
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/* MIPS special opcodes */ |
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enum { |
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/* Shifts */ |
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OPC_SLL = 0x00 | EXT_SPECIAL, |
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/* NOP is SLL r0, r0, 0 */ |
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/* SSNOP is SLL r0, r0, 1 */ |
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OPC_SRL = 0x02 | EXT_SPECIAL, |
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OPC_SRA = 0x03 | EXT_SPECIAL, |
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OPC_SLLV = 0x04 | EXT_SPECIAL, |
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OPC_SRLV = 0x06 | EXT_SPECIAL, |
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OPC_SRAV = 0x07 | EXT_SPECIAL, |
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/* Multiplication / division */ |
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OPC_MULT = 0x18 | EXT_SPECIAL, |
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OPC_MULTU = 0x19 | EXT_SPECIAL, |
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OPC_DIV = 0x1A | EXT_SPECIAL, |
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OPC_DIVU = 0x1B | EXT_SPECIAL, |
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/* 2 registers arithmetic / logic */ |
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OPC_ADD = 0x20 | EXT_SPECIAL, |
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OPC_ADDU = 0x21 | EXT_SPECIAL, |
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OPC_SUB = 0x22 | EXT_SPECIAL, |
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OPC_SUBU = 0x23 | EXT_SPECIAL, |
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OPC_AND = 0x24 | EXT_SPECIAL, |
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OPC_OR = 0x25 | EXT_SPECIAL, |
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OPC_XOR = 0x26 | EXT_SPECIAL, |
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OPC_NOR = 0x27 | EXT_SPECIAL, |
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OPC_SLT = 0x2A | EXT_SPECIAL, |
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OPC_SLTU = 0x2B | EXT_SPECIAL, |
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/* Jumps */ |
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OPC_JR = 0x08 | EXT_SPECIAL, |
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OPC_JALR = 0x09 | EXT_SPECIAL, |
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/* Traps */ |
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OPC_TGE = 0x30 | EXT_SPECIAL, |
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OPC_TGEU = 0x31 | EXT_SPECIAL, |
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OPC_TLT = 0x32 | EXT_SPECIAL, |
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OPC_TLTU = 0x33 | EXT_SPECIAL, |
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OPC_TEQ = 0x34 | EXT_SPECIAL, |
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OPC_TNE = 0x36 | EXT_SPECIAL, |
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/* HI / LO registers load & stores */ |
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|
OPC_MFHI = 0x10 | EXT_SPECIAL, |
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OPC_MTHI = 0x11 | EXT_SPECIAL, |
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OPC_MFLO = 0x12 | EXT_SPECIAL, |
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OPC_MTLO = 0x13 | EXT_SPECIAL, |
|
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/* Conditional moves */ |
|
|
OPC_MOVZ = 0x0A | EXT_SPECIAL, |
|
|
OPC_MOVN = 0x0B | EXT_SPECIAL, |
|
|
|
|
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OPC_MOVCI = 0x01 | EXT_SPECIAL, |
|
|
|
|
|
/* Special */ |
|
|
OPC_PMON = 0x05 | EXT_SPECIAL, |
|
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OPC_SYSCALL = 0x0C | EXT_SPECIAL, |
|
|
OPC_BREAK = 0x0D | EXT_SPECIAL, |
|
|
OPC_SYNC = 0x0F | EXT_SPECIAL, |
|
|
}; |
|
|
|
|
|
enum { |
|
|
/* Mutiply & xxx operations */ |
|
|
OPC_MADD = 0x00 | EXT_SPECIAL2, |
|
|
OPC_MADDU = 0x01 | EXT_SPECIAL2, |
|
|
OPC_MUL = 0x02 | EXT_SPECIAL2, |
|
|
OPC_MSUB = 0x04 | EXT_SPECIAL2, |
|
|
OPC_MSUBU = 0x05 | EXT_SPECIAL2, |
|
|
/* Misc */ |
|
|
OPC_CLZ = 0x20 | EXT_SPECIAL2, |
|
|
OPC_CLO = 0x21 | EXT_SPECIAL2, |
|
|
/* Special */ |
|
|
OPC_SDBBP = 0x3F | EXT_SPECIAL2, |
|
|
}; |
|
|
|
|
|
/* Branch REGIMM */ |
|
|
enum { |
|
|
OPC_BLTZ = 0x00 | EXT_REGIMM, |
|
|
OPC_BLTZL = 0x02 | EXT_REGIMM, |
|
|
OPC_BGEZ = 0x01 | EXT_REGIMM, |
|
|
OPC_BGEZL = 0x03 | EXT_REGIMM, |
|
|
OPC_BLTZAL = 0x10 | EXT_REGIMM, |
|
|
OPC_BLTZALL = 0x12 | EXT_REGIMM, |
|
|
OPC_BGEZAL = 0x11 | EXT_REGIMM, |
|
|
OPC_BGEZALL = 0x13 | EXT_REGIMM, |
|
|
OPC_TGEI = 0x08 | EXT_REGIMM, |
|
|
OPC_TGEIU = 0x09 | EXT_REGIMM, |
|
|
OPC_TLTI = 0x0A | EXT_REGIMM, |
|
|
OPC_TLTIU = 0x0B | EXT_REGIMM, |
|
|
OPC_TEQI = 0x0C | EXT_REGIMM, |
|
|
OPC_TNEI = 0x0E | EXT_REGIMM, |
|
|
}; |
|
|
|
|
|
enum { |
|
|
/* Coprocessor 0 (MMU) */ |
|
|
OPC_MFC0 = 0x00 | EXT_CP0, |
|
|
OPC_MTC0 = 0x04 | EXT_CP0, |
|
|
OPC_TLBR = 0x01 | EXT_CP0, |
|
|
OPC_TLBWI = 0x02 | EXT_CP0, |
|
|
OPC_TLBWR = 0x06 | EXT_CP0, |
|
|
OPC_TLBP = 0x08 | EXT_CP0, |
|
|
OPC_ERET = 0x18 | EXT_CP0, |
|
|
OPC_DERET = 0x1F | EXT_CP0, |
|
|
OPC_WAIT = 0x20 | EXT_CP0, |
|
|
}; |
|
|
|
|
243 |
int cpu_mips_exec(CPUMIPSState *s); |
int cpu_mips_exec(CPUMIPSState *s); |
244 |
CPUMIPSState *cpu_mips_init(void); |
CPUMIPSState *cpu_mips_init(void); |
245 |
uint32_t cpu_mips_get_clock (void); |
uint32_t cpu_mips_get_clock (void); |