1747 |
{ |
{ |
1748 |
if (s->cc_op != CC_OP_DYNAMIC) |
if (s->cc_op != CC_OP_DYNAMIC) |
1749 |
gen_op_set_cc_op(s->cc_op); |
gen_op_set_cc_op(s->cc_op); |
1750 |
|
if (s->tb->flags & HF_INHIBIT_IRQ_MASK) { |
1751 |
|
gen_op_reset_inhibit_irq(); |
1752 |
|
} |
1753 |
if (s->singlestep_enabled) { |
if (s->singlestep_enabled) { |
1754 |
gen_op_debug(); |
gen_op_debug(); |
1755 |
} else if (s->tf) { |
} else if (s->tf) { |
2388 |
gen_movl_seg_T0(s, reg, pc_start - s->cs_base); |
gen_movl_seg_T0(s, reg, pc_start - s->cs_base); |
2389 |
gen_pop_update(s); |
gen_pop_update(s); |
2390 |
if (reg == R_SS) { |
if (reg == R_SS) { |
2391 |
/* if reg == SS, inhibit interrupts/trace */ |
/* if reg == SS, inhibit interrupts/trace. */ |
2392 |
gen_op_set_inhibit_irq(); |
/* If several instructions disable interrupts, only the |
2393 |
|
_first_ does it */ |
2394 |
|
if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) |
2395 |
|
gen_op_set_inhibit_irq(); |
2396 |
s->tf = 0; |
s->tf = 0; |
2397 |
} |
} |
2398 |
if (s->is_jmp) { |
if (s->is_jmp) { |
2463 |
gen_movl_seg_T0(s, reg, pc_start - s->cs_base); |
gen_movl_seg_T0(s, reg, pc_start - s->cs_base); |
2464 |
if (reg == R_SS) { |
if (reg == R_SS) { |
2465 |
/* if reg == SS, inhibit interrupts/trace */ |
/* if reg == SS, inhibit interrupts/trace */ |
2466 |
gen_op_set_inhibit_irq(); |
/* If several instructions disable interrupts, only the |
2467 |
|
_first_ does it */ |
2468 |
|
if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) |
2469 |
|
gen_op_set_inhibit_irq(); |
2470 |
s->tf = 0; |
s->tf = 0; |
2471 |
} |
} |
2472 |
if (s->is_jmp) { |
if (s->is_jmp) { |
3185 |
gen_op_fpop(); |
gen_op_fpop(); |
3186 |
s->cc_op = CC_OP_EFLAGS; |
s->cc_op = CC_OP_EFLAGS; |
3187 |
break; |
break; |
3188 |
|
case 0x10 ... 0x13: /* fcmovxx */ |
3189 |
|
case 0x18 ... 0x1b: |
3190 |
|
{ |
3191 |
|
int op1; |
3192 |
|
const static uint8_t fcmov_cc[8] = { |
3193 |
|
(JCC_B << 1), |
3194 |
|
(JCC_Z << 1), |
3195 |
|
(JCC_BE << 1), |
3196 |
|
(JCC_P << 1), |
3197 |
|
}; |
3198 |
|
op1 = fcmov_cc[op & 3] | ((op >> 3) & 1); |
3199 |
|
gen_setcc(s, op1); |
3200 |
|
gen_op_fcmov_ST0_STN_T0(opreg); |
3201 |
|
} |
3202 |
|
break; |
3203 |
default: |
default: |
3204 |
goto illegal_op; |
goto illegal_op; |
3205 |
} |
} |
3754 |
gen_sti: |
gen_sti: |
3755 |
gen_op_sti(); |
gen_op_sti(); |
3756 |
/* interruptions are enabled only the first insn after sti */ |
/* interruptions are enabled only the first insn after sti */ |
3757 |
gen_op_set_inhibit_irq(); |
/* If several instructions disable interrupts, only the |
3758 |
|
_first_ does it */ |
3759 |
|
if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) |
3760 |
|
gen_op_set_inhibit_irq(); |
3761 |
/* give a chance to handle pending irqs */ |
/* give a chance to handle pending irqs */ |
3762 |
gen_op_jmp_im(s->pc - s->cs_base); |
gen_op_jmp_im(s->pc - s->cs_base); |
3763 |
gen_eob(s); |
gen_eob(s); |
4486 |
else |
else |
4487 |
dc->mem_index = 3; |
dc->mem_index = 3; |
4488 |
} |
} |
4489 |
dc->jmp_opt = !(dc->tf || env->singlestep_enabled |
dc->jmp_opt = !(dc->tf || env->singlestep_enabled || |
4490 |
|
(flags & HF_INHIBIT_IRQ_MASK) |
4491 |
#ifndef CONFIG_SOFTMMU |
#ifndef CONFIG_SOFTMMU |
4492 |
|| (flags & HF_SOFTMMU_MASK) |
|| (flags & HF_SOFTMMU_MASK) |
4493 |
#endif |
#endif |
4500 |
pc_ptr = pc_start; |
pc_ptr = pc_start; |
4501 |
lj = -1; |
lj = -1; |
4502 |
|
|
|
/* if irq were inhibited for the next instruction, we can disable |
|
|
them here as it is simpler (otherwise jumps would have to |
|
|
handled as special case) */ |
|
|
if (flags & HF_INHIBIT_IRQ_MASK) { |
|
|
gen_op_reset_inhibit_irq(); |
|
|
} |
|
4503 |
for(;;) { |
for(;;) { |
4504 |
if (env->nb_breakpoints > 0) { |
if (env->nb_breakpoints > 0) { |
4505 |
for(j = 0; j < env->nb_breakpoints; j++) { |
for(j = 0; j < env->nb_breakpoints; j++) { |
4526 |
break; |
break; |
4527 |
/* if single step mode, we generate only one instruction and |
/* if single step mode, we generate only one instruction and |
4528 |
generate an exception */ |
generate an exception */ |
4529 |
if (dc->tf || dc->singlestep_enabled) { |
/* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear |
4530 |
|
the flag and abort the translation to give the irqs a |
4531 |
|
change to be happen */ |
4532 |
|
if (dc->tf || dc->singlestep_enabled || |
4533 |
|
(flags & HF_INHIBIT_IRQ_MASK)) { |
4534 |
gen_op_jmp_im(pc_ptr - dc->cs_base); |
gen_op_jmp_im(pc_ptr - dc->cs_base); |
4535 |
gen_eob(dc); |
gen_eob(dc); |
4536 |
break; |
break; |