654 |
Reg *d, *s;\ |
Reg *d, *s;\ |
655 |
d = (Reg *)((char *)env + PARAM1);\ |
d = (Reg *)((char *)env + PARAM1);\ |
656 |
s = (Reg *)((char *)env + PARAM2);\ |
s = (Reg *)((char *)env + PARAM2);\ |
657 |
d->XMM_S(0) = F(d->XMM_S(0), s->XMM_S(0));\ |
d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0));\ |
658 |
d->XMM_S(1) = F(d->XMM_S(1), s->XMM_S(1));\ |
d->XMM_S(1) = F(32, d->XMM_S(1), s->XMM_S(1));\ |
659 |
d->XMM_S(2) = F(d->XMM_S(2), s->XMM_S(2));\ |
d->XMM_S(2) = F(32, d->XMM_S(2), s->XMM_S(2));\ |
660 |
d->XMM_S(3) = F(d->XMM_S(3), s->XMM_S(3));\ |
d->XMM_S(3) = F(32, d->XMM_S(3), s->XMM_S(3));\ |
661 |
}\ |
}\ |
662 |
\ |
\ |
663 |
void OPPROTO op_ ## name ## ss (void)\ |
void OPPROTO op_ ## name ## ss (void)\ |
665 |
Reg *d, *s;\ |
Reg *d, *s;\ |
666 |
d = (Reg *)((char *)env + PARAM1);\ |
d = (Reg *)((char *)env + PARAM1);\ |
667 |
s = (Reg *)((char *)env + PARAM2);\ |
s = (Reg *)((char *)env + PARAM2);\ |
668 |
d->XMM_S(0) = F(d->XMM_S(0), s->XMM_S(0));\ |
d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0));\ |
669 |
}\ |
}\ |
670 |
void OPPROTO op_ ## name ## pd (void)\ |
void OPPROTO op_ ## name ## pd (void)\ |
671 |
{\ |
{\ |
672 |
Reg *d, *s;\ |
Reg *d, *s;\ |
673 |
d = (Reg *)((char *)env + PARAM1);\ |
d = (Reg *)((char *)env + PARAM1);\ |
674 |
s = (Reg *)((char *)env + PARAM2);\ |
s = (Reg *)((char *)env + PARAM2);\ |
675 |
d->XMM_D(0) = F(d->XMM_D(0), s->XMM_D(0));\ |
d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0));\ |
676 |
d->XMM_D(1) = F(d->XMM_D(1), s->XMM_D(1));\ |
d->XMM_D(1) = F(64, d->XMM_D(1), s->XMM_D(1));\ |
677 |
}\ |
}\ |
678 |
\ |
\ |
679 |
void OPPROTO op_ ## name ## sd (void)\ |
void OPPROTO op_ ## name ## sd (void)\ |
681 |
Reg *d, *s;\ |
Reg *d, *s;\ |
682 |
d = (Reg *)((char *)env + PARAM1);\ |
d = (Reg *)((char *)env + PARAM1);\ |
683 |
s = (Reg *)((char *)env + PARAM2);\ |
s = (Reg *)((char *)env + PARAM2);\ |
684 |
d->XMM_D(0) = F(d->XMM_D(0), s->XMM_D(0));\ |
d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0));\ |
685 |
} |
} |
686 |
|
|
687 |
#define FPU_ADD(a, b) (a) + (b) |
#define FPU_ADD(size, a, b) float ## size ## _add(a, b, &env->sse_status) |
688 |
#define FPU_SUB(a, b) (a) - (b) |
#define FPU_SUB(size, a, b) float ## size ## _sub(a, b, &env->sse_status) |
689 |
#define FPU_MUL(a, b) (a) * (b) |
#define FPU_MUL(size, a, b) float ## size ## _mul(a, b, &env->sse_status) |
690 |
#define FPU_DIV(a, b) (a) / (b) |
#define FPU_DIV(size, a, b) float ## size ## _div(a, b, &env->sse_status) |
691 |
#define FPU_MIN(a, b) (a) < (b) ? (a) : (b) |
#define FPU_MIN(size, a, b) (a) < (b) ? (a) : (b) |
692 |
#define FPU_MAX(a, b) (a) > (b) ? (a) : (b) |
#define FPU_MAX(size, a, b) (a) > (b) ? (a) : (b) |
693 |
#define FPU_SQRT(a, b) helper_sqrt(b) |
#define FPU_SQRT(size, a, b) float ## size ## _sqrt(b, &env->sse_status) |
694 |
|
|
695 |
SSE_OP_S(add, FPU_ADD) |
SSE_OP_S(add, FPU_ADD) |
696 |
SSE_OP_S(sub, FPU_SUB) |
SSE_OP_S(sub, FPU_SUB) |
710 |
s = (Reg *)((char *)env + PARAM2); |
s = (Reg *)((char *)env + PARAM2); |
711 |
s0 = s->XMM_S(0); |
s0 = s->XMM_S(0); |
712 |
s1 = s->XMM_S(1); |
s1 = s->XMM_S(1); |
713 |
d->XMM_D(0) = float32_to_float64(s0); |
d->XMM_D(0) = float32_to_float64(s0, &env->sse_status); |
714 |
d->XMM_D(1) = float32_to_float64(s1); |
d->XMM_D(1) = float32_to_float64(s1, &env->sse_status); |
715 |
} |
} |
716 |
|
|
717 |
void OPPROTO op_cvtpd2ps(void) |
void OPPROTO op_cvtpd2ps(void) |
719 |
Reg *d, *s; |
Reg *d, *s; |
720 |
d = (Reg *)((char *)env + PARAM1); |
d = (Reg *)((char *)env + PARAM1); |
721 |
s = (Reg *)((char *)env + PARAM2); |
s = (Reg *)((char *)env + PARAM2); |
722 |
d->XMM_S(0) = float64_to_float32(s->XMM_D(0)); |
d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status); |
723 |
d->XMM_S(1) = float64_to_float32(s->XMM_D(1)); |
d->XMM_S(1) = float64_to_float32(s->XMM_D(1), &env->sse_status); |
724 |
d->Q(1) = 0; |
d->Q(1) = 0; |
725 |
} |
} |
726 |
|
|
729 |
Reg *d, *s; |
Reg *d, *s; |
730 |
d = (Reg *)((char *)env + PARAM1); |
d = (Reg *)((char *)env + PARAM1); |
731 |
s = (Reg *)((char *)env + PARAM2); |
s = (Reg *)((char *)env + PARAM2); |
732 |
d->XMM_D(0) = float32_to_float64(s->XMM_S(0)); |
d->XMM_D(0) = float32_to_float64(s->XMM_S(0), &env->sse_status); |
733 |
} |
} |
734 |
|
|
735 |
void OPPROTO op_cvtsd2ss(void) |
void OPPROTO op_cvtsd2ss(void) |
737 |
Reg *d, *s; |
Reg *d, *s; |
738 |
d = (Reg *)((char *)env + PARAM1); |
d = (Reg *)((char *)env + PARAM1); |
739 |
s = (Reg *)((char *)env + PARAM2); |
s = (Reg *)((char *)env + PARAM2); |
740 |
d->XMM_S(0) = float64_to_float32(s->XMM_D(0)); |
d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status); |
741 |
} |
} |
742 |
|
|
743 |
/* integer to float */ |
/* integer to float */ |
745 |
{ |
{ |
746 |
XMMReg *d = (XMMReg *)((char *)env + PARAM1); |
XMMReg *d = (XMMReg *)((char *)env + PARAM1); |
747 |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
748 |
d->XMM_S(0) = int32_to_float32(s->XMM_L(0)); |
d->XMM_S(0) = int32_to_float32(s->XMM_L(0), &env->sse_status); |
749 |
d->XMM_S(1) = int32_to_float32(s->XMM_L(1)); |
d->XMM_S(1) = int32_to_float32(s->XMM_L(1), &env->sse_status); |
750 |
d->XMM_S(2) = int32_to_float32(s->XMM_L(2)); |
d->XMM_S(2) = int32_to_float32(s->XMM_L(2), &env->sse_status); |
751 |
d->XMM_S(3) = int32_to_float32(s->XMM_L(3)); |
d->XMM_S(3) = int32_to_float32(s->XMM_L(3), &env->sse_status); |
752 |
} |
} |
753 |
|
|
754 |
void OPPROTO op_cvtdq2pd(void) |
void OPPROTO op_cvtdq2pd(void) |
758 |
int32_t l0, l1; |
int32_t l0, l1; |
759 |
l0 = (int32_t)s->XMM_L(0); |
l0 = (int32_t)s->XMM_L(0); |
760 |
l1 = (int32_t)s->XMM_L(1); |
l1 = (int32_t)s->XMM_L(1); |
761 |
d->XMM_D(0) = int32_to_float64(l0); |
d->XMM_D(0) = int32_to_float64(l0, &env->sse_status); |
762 |
d->XMM_D(1) = int32_to_float64(l1); |
d->XMM_D(1) = int32_to_float64(l1, &env->sse_status); |
763 |
} |
} |
764 |
|
|
765 |
void OPPROTO op_cvtpi2ps(void) |
void OPPROTO op_cvtpi2ps(void) |
766 |
{ |
{ |
767 |
XMMReg *d = (Reg *)((char *)env + PARAM1); |
XMMReg *d = (Reg *)((char *)env + PARAM1); |
768 |
MMXReg *s = (MMXReg *)((char *)env + PARAM2); |
MMXReg *s = (MMXReg *)((char *)env + PARAM2); |
769 |
d->XMM_S(0) = int32_to_float32(s->MMX_L(0)); |
d->XMM_S(0) = int32_to_float32(s->MMX_L(0), &env->sse_status); |
770 |
d->XMM_S(1) = int32_to_float32(s->MMX_L(1)); |
d->XMM_S(1) = int32_to_float32(s->MMX_L(1), &env->sse_status); |
771 |
} |
} |
772 |
|
|
773 |
void OPPROTO op_cvtpi2pd(void) |
void OPPROTO op_cvtpi2pd(void) |
774 |
{ |
{ |
775 |
XMMReg *d = (Reg *)((char *)env + PARAM1); |
XMMReg *d = (Reg *)((char *)env + PARAM1); |
776 |
MMXReg *s = (MMXReg *)((char *)env + PARAM2); |
MMXReg *s = (MMXReg *)((char *)env + PARAM2); |
777 |
d->XMM_D(0) = int32_to_float64(s->MMX_L(0)); |
d->XMM_D(0) = int32_to_float64(s->MMX_L(0), &env->sse_status); |
778 |
d->XMM_D(1) = int32_to_float64(s->MMX_L(1)); |
d->XMM_D(1) = int32_to_float64(s->MMX_L(1), &env->sse_status); |
779 |
} |
} |
780 |
|
|
781 |
void OPPROTO op_cvtsi2ss(void) |
void OPPROTO op_cvtsi2ss(void) |
782 |
{ |
{ |
783 |
XMMReg *d = (Reg *)((char *)env + PARAM1); |
XMMReg *d = (Reg *)((char *)env + PARAM1); |
784 |
d->XMM_S(0) = int32_to_float32(T0); |
d->XMM_S(0) = int32_to_float32(T0, &env->sse_status); |
785 |
} |
} |
786 |
|
|
787 |
void OPPROTO op_cvtsi2sd(void) |
void OPPROTO op_cvtsi2sd(void) |
788 |
{ |
{ |
789 |
XMMReg *d = (Reg *)((char *)env + PARAM1); |
XMMReg *d = (Reg *)((char *)env + PARAM1); |
790 |
d->XMM_D(0) = int32_to_float64(T0); |
d->XMM_D(0) = int32_to_float64(T0, &env->sse_status); |
791 |
} |
} |
792 |
|
|
793 |
#ifdef TARGET_X86_64 |
#ifdef TARGET_X86_64 |
794 |
void OPPROTO op_cvtsq2ss(void) |
void OPPROTO op_cvtsq2ss(void) |
795 |
{ |
{ |
796 |
XMMReg *d = (Reg *)((char *)env + PARAM1); |
XMMReg *d = (Reg *)((char *)env + PARAM1); |
797 |
d->XMM_S(0) = int64_to_float32(T0); |
d->XMM_S(0) = int64_to_float32(T0, &env->sse_status); |
798 |
} |
} |
799 |
|
|
800 |
void OPPROTO op_cvtsq2sd(void) |
void OPPROTO op_cvtsq2sd(void) |
801 |
{ |
{ |
802 |
XMMReg *d = (Reg *)((char *)env + PARAM1); |
XMMReg *d = (Reg *)((char *)env + PARAM1); |
803 |
d->XMM_D(0) = int64_to_float64(T0); |
d->XMM_D(0) = int64_to_float64(T0, &env->sse_status); |
804 |
} |
} |
805 |
#endif |
#endif |
806 |
|
|
809 |
{ |
{ |
810 |
XMMReg *d = (XMMReg *)((char *)env + PARAM1); |
XMMReg *d = (XMMReg *)((char *)env + PARAM1); |
811 |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
812 |
d->XMM_L(0) = lrint(s->XMM_S(0)); |
d->XMM_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status); |
813 |
d->XMM_L(1) = lrint(s->XMM_S(1)); |
d->XMM_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status); |
814 |
d->XMM_L(2) = lrint(s->XMM_S(2)); |
d->XMM_L(2) = float32_to_int32(s->XMM_S(2), &env->sse_status); |
815 |
d->XMM_L(3) = lrint(s->XMM_S(3)); |
d->XMM_L(3) = float32_to_int32(s->XMM_S(3), &env->sse_status); |
816 |
} |
} |
817 |
|
|
818 |
void OPPROTO op_cvtpd2dq(void) |
void OPPROTO op_cvtpd2dq(void) |
819 |
{ |
{ |
820 |
XMMReg *d = (XMMReg *)((char *)env + PARAM1); |
XMMReg *d = (XMMReg *)((char *)env + PARAM1); |
821 |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
822 |
d->XMM_L(0) = lrint(s->XMM_D(0)); |
d->XMM_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status); |
823 |
d->XMM_L(1) = lrint(s->XMM_D(1)); |
d->XMM_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status); |
824 |
d->XMM_Q(1) = 0; |
d->XMM_Q(1) = 0; |
825 |
} |
} |
826 |
|
|
828 |
{ |
{ |
829 |
MMXReg *d = (MMXReg *)((char *)env + PARAM1); |
MMXReg *d = (MMXReg *)((char *)env + PARAM1); |
830 |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
831 |
d->MMX_L(0) = lrint(s->XMM_S(0)); |
d->MMX_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status); |
832 |
d->MMX_L(1) = lrint(s->XMM_S(1)); |
d->MMX_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status); |
833 |
} |
} |
834 |
|
|
835 |
void OPPROTO op_cvtpd2pi(void) |
void OPPROTO op_cvtpd2pi(void) |
836 |
{ |
{ |
837 |
MMXReg *d = (MMXReg *)((char *)env + PARAM1); |
MMXReg *d = (MMXReg *)((char *)env + PARAM1); |
838 |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
839 |
d->MMX_L(0) = lrint(s->XMM_D(0)); |
d->MMX_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status); |
840 |
d->MMX_L(1) = lrint(s->XMM_D(1)); |
d->MMX_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status); |
841 |
} |
} |
842 |
|
|
843 |
void OPPROTO op_cvtss2si(void) |
void OPPROTO op_cvtss2si(void) |
844 |
{ |
{ |
845 |
XMMReg *s = (XMMReg *)((char *)env + PARAM1); |
XMMReg *s = (XMMReg *)((char *)env + PARAM1); |
846 |
T0 = (int32_t)lrint(s->XMM_S(0)); |
T0 = float32_to_int32(s->XMM_S(0), &env->sse_status); |
847 |
} |
} |
848 |
|
|
849 |
void OPPROTO op_cvtsd2si(void) |
void OPPROTO op_cvtsd2si(void) |
850 |
{ |
{ |
851 |
XMMReg *s = (XMMReg *)((char *)env + PARAM1); |
XMMReg *s = (XMMReg *)((char *)env + PARAM1); |
852 |
T0 = (int32_t)lrint(s->XMM_D(0)); |
T0 = float64_to_int32(s->XMM_D(0), &env->sse_status); |
853 |
} |
} |
854 |
|
|
855 |
#ifdef TARGET_X86_64 |
#ifdef TARGET_X86_64 |
856 |
void OPPROTO op_cvtss2sq(void) |
void OPPROTO op_cvtss2sq(void) |
857 |
{ |
{ |
858 |
XMMReg *s = (XMMReg *)((char *)env + PARAM1); |
XMMReg *s = (XMMReg *)((char *)env + PARAM1); |
859 |
T0 = llrint(s->XMM_S(0)); |
T0 = float32_to_int64(s->XMM_S(0), &env->sse_status); |
860 |
} |
} |
861 |
|
|
862 |
void OPPROTO op_cvtsd2sq(void) |
void OPPROTO op_cvtsd2sq(void) |
863 |
{ |
{ |
864 |
XMMReg *s = (XMMReg *)((char *)env + PARAM1); |
XMMReg *s = (XMMReg *)((char *)env + PARAM1); |
865 |
T0 = llrint(s->XMM_D(0)); |
T0 = float64_to_int64(s->XMM_D(0), &env->sse_status); |
866 |
} |
} |
867 |
#endif |
#endif |
868 |
|
|
871 |
{ |
{ |
872 |
XMMReg *d = (XMMReg *)((char *)env + PARAM1); |
XMMReg *d = (XMMReg *)((char *)env + PARAM1); |
873 |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
874 |
d->XMM_L(0) = (int32_t)s->XMM_S(0); |
d->XMM_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); |
875 |
d->XMM_L(1) = (int32_t)s->XMM_S(1); |
d->XMM_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status); |
876 |
d->XMM_L(2) = (int32_t)s->XMM_S(2); |
d->XMM_L(2) = float32_to_int32_round_to_zero(s->XMM_S(2), &env->sse_status); |
877 |
d->XMM_L(3) = (int32_t)s->XMM_S(3); |
d->XMM_L(3) = float32_to_int32_round_to_zero(s->XMM_S(3), &env->sse_status); |
878 |
} |
} |
879 |
|
|
880 |
void OPPROTO op_cvttpd2dq(void) |
void OPPROTO op_cvttpd2dq(void) |
881 |
{ |
{ |
882 |
XMMReg *d = (XMMReg *)((char *)env + PARAM1); |
XMMReg *d = (XMMReg *)((char *)env + PARAM1); |
883 |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
884 |
d->XMM_L(0) = (int32_t)s->XMM_D(0); |
d->XMM_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); |
885 |
d->XMM_L(1) = (int32_t)s->XMM_D(1); |
d->XMM_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status); |
886 |
d->XMM_Q(1) = 0; |
d->XMM_Q(1) = 0; |
887 |
} |
} |
888 |
|
|
890 |
{ |
{ |
891 |
MMXReg *d = (MMXReg *)((char *)env + PARAM1); |
MMXReg *d = (MMXReg *)((char *)env + PARAM1); |
892 |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
893 |
d->MMX_L(0) = (int32_t)(s->XMM_S(0)); |
d->MMX_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); |
894 |
d->MMX_L(1) = (int32_t)(s->XMM_S(1)); |
d->MMX_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status); |
895 |
} |
} |
896 |
|
|
897 |
void OPPROTO op_cvttpd2pi(void) |
void OPPROTO op_cvttpd2pi(void) |
898 |
{ |
{ |
899 |
MMXReg *d = (MMXReg *)((char *)env + PARAM1); |
MMXReg *d = (MMXReg *)((char *)env + PARAM1); |
900 |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
XMMReg *s = (XMMReg *)((char *)env + PARAM2); |
901 |
d->MMX_L(0) = (int32_t)(s->XMM_D(0)); |
d->MMX_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); |
902 |
d->MMX_L(1) = (int32_t)(s->XMM_D(1)); |
d->MMX_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status); |
903 |
} |
} |
904 |
|
|
905 |
void OPPROTO op_cvttss2si(void) |
void OPPROTO op_cvttss2si(void) |
906 |
{ |
{ |
907 |
XMMReg *s = (XMMReg *)((char *)env + PARAM1); |
XMMReg *s = (XMMReg *)((char *)env + PARAM1); |
908 |
T0 = (int32_t)(s->XMM_S(0)); |
T0 = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); |
909 |
} |
} |
910 |
|
|
911 |
void OPPROTO op_cvttsd2si(void) |
void OPPROTO op_cvttsd2si(void) |
912 |
{ |
{ |
913 |
XMMReg *s = (XMMReg *)((char *)env + PARAM1); |
XMMReg *s = (XMMReg *)((char *)env + PARAM1); |
914 |
T0 = (int32_t)(s->XMM_D(0)); |
T0 = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); |
915 |
} |
} |
916 |
|
|
917 |
#ifdef TARGET_X86_64 |
#ifdef TARGET_X86_64 |
918 |
void OPPROTO op_cvttss2sq(void) |
void OPPROTO op_cvttss2sq(void) |
919 |
{ |
{ |
920 |
XMMReg *s = (XMMReg *)((char *)env + PARAM1); |
XMMReg *s = (XMMReg *)((char *)env + PARAM1); |
921 |
T0 = (int64_t)(s->XMM_S(0)); |
T0 = float32_to_int64_round_to_zero(s->XMM_S(0), &env->sse_status); |
922 |
} |
} |
923 |
|
|
924 |
void OPPROTO op_cvttsd2sq(void) |
void OPPROTO op_cvttsd2sq(void) |
925 |
{ |
{ |
926 |
XMMReg *s = (XMMReg *)((char *)env + PARAM1); |
XMMReg *s = (XMMReg *)((char *)env + PARAM1); |
927 |
T0 = (int64_t)(s->XMM_D(0)); |
T0 = float64_to_int64_round_to_zero(s->XMM_D(0), &env->sse_status); |
928 |
} |
} |
929 |
#endif |
#endif |
930 |
|
|