1334 |
ECX = env->cpuid_model[(index - 0x80000002) * 4 + 2]; |
ECX = env->cpuid_model[(index - 0x80000002) * 4 + 2]; |
1335 |
EDX = env->cpuid_model[(index - 0x80000002) * 4 + 3]; |
EDX = env->cpuid_model[(index - 0x80000002) * 4 + 3]; |
1336 |
break; |
break; |
1337 |
|
case 0x80000005: |
1338 |
|
/* cache info (L1 cache) */ |
1339 |
|
EAX = 0x01ff01ff; |
1340 |
|
EBX = 0x01ff01ff; |
1341 |
|
ECX = 0x40020140; |
1342 |
|
EDX = 0x40020140; |
1343 |
|
break; |
1344 |
|
case 0x80000006: |
1345 |
|
/* cache info (L2 cache) */ |
1346 |
|
EAX = 0; |
1347 |
|
EBX = 0x42004200; |
1348 |
|
ECX = 0x02008140; |
1349 |
|
EDX = 0; |
1350 |
|
break; |
1351 |
case 0x80000008: |
case 0x80000008: |
1352 |
/* virtual & phys address size in low 2 bytes. */ |
/* virtual & phys address size in low 2 bytes. */ |
1353 |
EAX = 0x00003028; |
EAX = 0x00003028; |
1397 |
} |
} |
1398 |
} |
} |
1399 |
|
|
1400 |
|
#ifdef TARGET_X86_64 |
1401 |
|
void helper_enter64_level(int level, int data64) |
1402 |
|
{ |
1403 |
|
target_ulong esp, ebp; |
1404 |
|
ebp = EBP; |
1405 |
|
esp = ESP; |
1406 |
|
|
1407 |
|
if (data64) { |
1408 |
|
/* 64 bit */ |
1409 |
|
esp -= 8; |
1410 |
|
while (--level) { |
1411 |
|
esp -= 8; |
1412 |
|
ebp -= 8; |
1413 |
|
stq(esp, ldq(ebp)); |
1414 |
|
} |
1415 |
|
esp -= 8; |
1416 |
|
stq(esp, T1); |
1417 |
|
} else { |
1418 |
|
/* 16 bit */ |
1419 |
|
esp -= 2; |
1420 |
|
while (--level) { |
1421 |
|
esp -= 2; |
1422 |
|
ebp -= 2; |
1423 |
|
stw(esp, lduw(ebp)); |
1424 |
|
} |
1425 |
|
esp -= 2; |
1426 |
|
stw(esp, T1); |
1427 |
|
} |
1428 |
|
} |
1429 |
|
#endif |
1430 |
|
|
1431 |
void helper_lldt_T0(void) |
void helper_lldt_T0(void) |
1432 |
{ |
{ |
1433 |
int selector; |
int selector; |
2008 |
#endif |
#endif |
2009 |
sp_mask = get_sp_mask(env->segs[R_SS].flags); |
sp_mask = get_sp_mask(env->segs[R_SS].flags); |
2010 |
sp = ESP; |
sp = ESP; |
2011 |
|
/* XXX: ssp is zero in 64 bit ? */ |
2012 |
ssp = env->segs[R_SS].base; |
ssp = env->segs[R_SS].base; |
2013 |
new_eflags = 0; /* avoid warning */ |
new_eflags = 0; /* avoid warning */ |
2014 |
#ifdef TARGET_X86_64 |
#ifdef TARGET_X86_64 |
2317 |
env->dr[reg] = T0; |
env->dr[reg] = T0; |
2318 |
} |
} |
2319 |
|
|
2320 |
void helper_invlpg(unsigned int addr) |
void helper_invlpg(target_ulong addr) |
2321 |
{ |
{ |
2322 |
cpu_x86_flush_tlb(env, addr); |
cpu_x86_flush_tlb(env, addr); |
2323 |
} |
} |
2378 |
case MSR_STAR: |
case MSR_STAR: |
2379 |
env->star = val; |
env->star = val; |
2380 |
break; |
break; |
2381 |
|
case MSR_PAT: |
2382 |
|
env->pat = val; |
2383 |
|
break; |
2384 |
#ifdef TARGET_X86_64 |
#ifdef TARGET_X86_64 |
2385 |
case MSR_LSTAR: |
case MSR_LSTAR: |
2386 |
env->lstar = val; |
env->lstar = val; |
2429 |
case MSR_STAR: |
case MSR_STAR: |
2430 |
val = env->star; |
val = env->star; |
2431 |
break; |
break; |
2432 |
|
case MSR_PAT: |
2433 |
|
val = env->pat; |
2434 |
|
break; |
2435 |
#ifdef TARGET_X86_64 |
#ifdef TARGET_X86_64 |
2436 |
case MSR_LSTAR: |
case MSR_LSTAR: |
2437 |
val = env->lstar; |
val = env->lstar; |