/[qemu]/qemu/target-arm/op.c
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revision 1.15 by bellard, Sun Oct 30 21:39:18 2005 UTC revision 1.16 by bellard, Sat Nov 26 10:38:39 2005 UTC
# Line 101  void OPPROTO op_movl_T0_im(void) Line 101  void OPPROTO op_movl_T0_im(void)
101      T0 = PARAM1;      T0 = PARAM1;
102  }  }
103    
104    void OPPROTO op_movl_T0_T1(void)
105    {
106        T0 = T1;
107    }
108    
109  void OPPROTO op_movl_T1_im(void)  void OPPROTO op_movl_T1_im(void)
110  {  {
111      T1 = PARAM1;      T1 = PARAM1;
# Line 361  void OPPROTO op_exit_tb(void) Line 366  void OPPROTO op_exit_tb(void)
366      EXIT_TB();      EXIT_TB();
367  }  }
368    
369  void OPPROTO op_movl_T0_psr(void)  void OPPROTO op_movl_T0_cpsr(void)
370  {  {
371      T0 = compute_cpsr();      T0 = cpsr_read(env);
372        FORCE_RET();
373  }  }
374    
375  /* NOTE: N = 1 and Z = 1 cannot be stored currently */  void OPPROTO op_movl_T0_spsr(void)
 void OPPROTO op_movl_psr_T0(void)  
376  {  {
377      unsigned int psr;      T0 = env->spsr;
378      psr = T0;  }
379      env->CF = (psr >> 29) & 1;  
380      env->NZF = (psr & 0xc0000000) ^ 0x40000000;  void OPPROTO op_movl_spsr_T0(void)
381      env->VF = (psr << 3) & 0x80000000;  {
382      /* for user mode we do not update other state info */      uint32_t mask = PARAM1;
383        env->spsr = (env->spsr & ~mask) | (T0 & mask);
384    }
385    
386    void OPPROTO op_movl_cpsr_T0(void)
387    {
388        cpsr_write(env, T0, PARAM1);
389        FORCE_RET();
390  }  }
391    
392  void OPPROTO op_mul_T0_T1(void)  void OPPROTO op_mul_T0_T1(void)
# Line 433  void OPPROTO op_logicq_cc(void) Line 445  void OPPROTO op_logicq_cc(void)
445    
446  /* memory access */  /* memory access */
447    
448  void OPPROTO op_ldub_T0_T1(void)  #define MEMSUFFIX _raw
449  {  #include "op_mem.h"
     T0 = ldub((void *)T1);  
 }  
   
 void OPPROTO op_ldsb_T0_T1(void)  
 {  
     T0 = ldsb((void *)T1);  
 }  
   
 void OPPROTO op_lduw_T0_T1(void)  
 {  
     T0 = lduw((void *)T1);  
 }  
   
 void OPPROTO op_ldsw_T0_T1(void)  
 {  
     T0 = ldsw((void *)T1);  
 }  
   
 void OPPROTO op_ldl_T0_T1(void)  
 {  
     T0 = ldl((void *)T1);  
 }  
   
 void OPPROTO op_stb_T0_T1(void)  
 {  
     stb((void *)T1, T0);  
 }  
   
 void OPPROTO op_stw_T0_T1(void)  
 {  
     stw((void *)T1, T0);  
 }  
   
 void OPPROTO op_stl_T0_T1(void)  
 {  
     stl((void *)T1, T0);  
 }  
   
 void OPPROTO op_swpb_T0_T1(void)  
 {  
     int tmp;  
450    
451      cpu_lock();  #if !defined(CONFIG_USER_ONLY)
452      tmp = ldub((void *)T1);  #define MEMSUFFIX _user
453      stb((void *)T1, T0);  #include "op_mem.h"
454      T0 = tmp;  #define MEMSUFFIX _kernel
455      cpu_unlock();  #include "op_mem.h"
456  }  #endif
   
 void OPPROTO op_swpl_T0_T1(void)  
 {  
     int tmp;  
   
     cpu_lock();  
     tmp = ldl((void *)T1);  
     stl((void *)T1, T0);  
     T0 = tmp;  
     cpu_unlock();  
 }  
457    
458  /* shifts */  /* shifts */
459    
# Line 744  void OPPROTO op_sarl_T0_im(void) Line 704  void OPPROTO op_sarl_T0_im(void)
704      T0 = (int32_t)T0 >> PARAM1;      T0 = (int32_t)T0 >> PARAM1;
705  }  }
706    
707  /* 16->32 Sign extend */  /* Sign/zero extend */
708  void OPPROTO op_sxl_T0(void)  void OPPROTO op_sxth_T0(void)
709  {  {
710    T0 = (int16_t)T0;    T0 = (int16_t)T0;
711  }  }
712    
713  void OPPROTO op_sxl_T1(void)  void OPPROTO op_sxth_T1(void)
714  {  {
715    T1 = (int16_t)T1;    T1 = (int16_t)T1;
716  }  }
717    
718    void OPPROTO op_sxtb_T1(void)
719    {
720        T1 = (int8_t)T1;
721    }
722    
723    void OPPROTO op_uxtb_T1(void)
724    {
725        T1 = (uint8_t)T1;
726    }
727    
728    void OPPROTO op_uxth_T1(void)
729    {
730        T1 = (uint16_t)T1;
731    }
732    
733    void OPPROTO op_sxtb16_T1(void)
734    {
735        uint32_t res;
736        res = (uint16_t)(int8_t)T1;
737        res |= (uint32_t)(int8_t)(T1 >> 16) << 16;
738        T1 = res;
739    }
740    
741    void OPPROTO op_uxtb16_T1(void)
742    {
743        uint32_t res;
744        res = (uint16_t)(uint8_t)T1;
745        res |= (uint32_t)(uint8_t)(T1 >> 16) << 16;
746        T1 = res;
747    }
748    
749  #define SIGNBIT (uint32_t)0x80000000  #define SIGNBIT (uint32_t)0x80000000
750  /* saturating arithmetic  */  /* saturating arithmetic  */
751  void OPPROTO op_addl_T0_T1_setq(void)  void OPPROTO op_addl_T0_T1_setq(void)
# Line 1128  void OPPROTO op_vfp_mdrr(void) Line 1119  void OPPROTO op_vfp_mdrr(void)
1119      FT0d = u.d;      FT0d = u.d;
1120  }  }
1121    
1122  /* Floating point load/store.  Address is in T1 */  /* Copy the most significant bit to T0 to all bits of T1.  */
1123  void OPPROTO op_vfp_lds(void)  void OPPROTO op_signbit_T1_T0(void)
1124  {  {
1125      FT0s = ldfl((void *)T1);      T1 = (int32_t)T0 >> 31;
1126  }  }
1127    
1128  void OPPROTO op_vfp_ldd(void)  void OPPROTO op_movl_cp15_T0(void)
1129  {  {
1130      FT0d = ldfq((void *)T1);      helper_set_cp15(env, PARAM1, T0);
1131        FORCE_RET();
1132  }  }
1133    
1134  void OPPROTO op_vfp_sts(void)  void OPPROTO op_movl_T0_cp15(void)
1135  {  {
1136      stfl((void *)T1, FT0s);      T0 = helper_get_cp15(env, PARAM1);
1137        FORCE_RET();
1138  }  }
1139    
1140  void OPPROTO op_vfp_std(void)  /* Access to user mode registers from privileged modes.  */
1141    void OPPROTO op_movl_T0_user(void)
1142  {  {
1143      stfq((void *)T1, FT0d);      int regno = PARAM1;
1144        if (regno == 13) {
1145            T0 = env->banked_r13[0];
1146        } else if (regno == 14) {
1147            T0 = env->banked_r14[0];
1148        } else if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
1149            T0 = env->usr_regs[regno - 8];
1150        } else {
1151            T0 = env->regs[regno];
1152        }
1153        FORCE_RET();
1154    }
1155    
1156    
1157    void OPPROTO op_movl_user_T0(void)
1158    {
1159        int regno = PARAM1;
1160        if (regno == 13) {
1161            env->banked_r13[0] = T0;
1162        } else if (regno == 14) {
1163            env->banked_r14[0] = T0;
1164        } else if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
1165            env->usr_regs[regno - 8] = T0;
1166        } else {
1167            env->regs[regno] = T0;
1168        }
1169        FORCE_RET();
1170  }  }

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