35 |
precision respectively. |
precision respectively. |
36 |
Doing runtime conversions is tricky because VFP registers may contain |
Doing runtime conversions is tricky because VFP registers may contain |
37 |
integer values (eg. as the result of a FTOSI instruction). |
integer values (eg. as the result of a FTOSI instruction). |
38 |
A double precision register load/store must also load/store the |
s<2n> maps to the least significant half of d<n> |
39 |
corresponding single precision pair, although it is undefined how |
s<2n+1> maps to the most significant half of d<n> |
40 |
these overlap. */ |
*/ |
41 |
|
|
42 |
typedef struct CPUARMState { |
typedef struct CPUARMState { |
43 |
uint32_t regs[16]; |
uint32_t regs[16]; |
71 |
memory was written */ |
memory was written */ |
72 |
/* VFP coprocessor state. */ |
/* VFP coprocessor state. */ |
73 |
struct { |
struct { |
74 |
union { |
float64 regs[16]; |
|
float32 s[32]; |
|
|
float64 d[16]; |
|
|
} regs; |
|
75 |
|
|
76 |
/* We store these fpcsr fields separately for convenience. */ |
/* We store these fpcsr fields separately for convenience. */ |
77 |
int vec_len; |
int vec_len; |