64 |
|
|
65 |
static void monitor_start_input(void); |
static void monitor_start_input(void); |
66 |
|
|
67 |
|
CPUState *mon_cpu = NULL; |
68 |
|
|
69 |
void term_flush(void) |
void term_flush(void) |
70 |
{ |
{ |
71 |
if (term_outbuf_index > 0) { |
if (term_outbuf_index > 0) { |
203 |
bdrv_info(); |
bdrv_info(); |
204 |
} |
} |
205 |
|
|
206 |
|
/* get the current CPU defined by the user */ |
207 |
|
int mon_set_cpu(int cpu_index) |
208 |
|
{ |
209 |
|
CPUState *env; |
210 |
|
|
211 |
|
for(env = first_cpu; env != NULL; env = env->next_cpu) { |
212 |
|
if (env->cpu_index == cpu_index) { |
213 |
|
mon_cpu = env; |
214 |
|
return 0; |
215 |
|
} |
216 |
|
} |
217 |
|
return -1; |
218 |
|
} |
219 |
|
|
220 |
|
CPUState *mon_get_cpu(void) |
221 |
|
{ |
222 |
|
if (!mon_cpu) { |
223 |
|
mon_set_cpu(0); |
224 |
|
} |
225 |
|
return mon_cpu; |
226 |
|
} |
227 |
|
|
228 |
static void do_info_registers(void) |
static void do_info_registers(void) |
229 |
{ |
{ |
230 |
|
CPUState *env; |
231 |
|
env = mon_get_cpu(); |
232 |
|
if (!env) |
233 |
|
return; |
234 |
#ifdef TARGET_I386 |
#ifdef TARGET_I386 |
235 |
cpu_dump_state(cpu_single_env, NULL, monitor_fprintf, |
cpu_dump_state(env, NULL, monitor_fprintf, |
236 |
X86_DUMP_FPU); |
X86_DUMP_FPU); |
237 |
#else |
#else |
238 |
cpu_dump_state(cpu_single_env, NULL, monitor_fprintf, |
cpu_dump_state(env, NULL, monitor_fprintf, |
239 |
0); |
0); |
240 |
#endif |
#endif |
241 |
} |
} |
242 |
|
|
243 |
|
static void do_info_cpus(void) |
244 |
|
{ |
245 |
|
CPUState *env; |
246 |
|
|
247 |
|
/* just to set the default cpu if not already done */ |
248 |
|
mon_get_cpu(); |
249 |
|
|
250 |
|
for(env = first_cpu; env != NULL; env = env->next_cpu) { |
251 |
|
term_printf("%c CPU #%d:", |
252 |
|
(env == mon_cpu) ? '*' : ' ', |
253 |
|
env->cpu_index); |
254 |
|
#if defined(TARGET_I386) |
255 |
|
term_printf(" pc=0x" TARGET_FMT_lx, env->eip + env->segs[R_CS].base); |
256 |
|
if (env->cpu_halted) |
257 |
|
term_printf(" (halted)"); |
258 |
|
#endif |
259 |
|
term_printf("\n"); |
260 |
|
} |
261 |
|
} |
262 |
|
|
263 |
|
static void do_cpu_set(int index) |
264 |
|
{ |
265 |
|
if (mon_set_cpu(index) < 0) |
266 |
|
term_printf("Invalid CPU index\n"); |
267 |
|
} |
268 |
|
|
269 |
static void do_info_jit(void) |
static void do_info_jit(void) |
270 |
{ |
{ |
271 |
dump_exec_info(NULL, monitor_fprintf); |
dump_exec_info(NULL, monitor_fprintf); |
435 |
static void memory_dump(int count, int format, int wsize, |
static void memory_dump(int count, int format, int wsize, |
436 |
target_ulong addr, int is_physical) |
target_ulong addr, int is_physical) |
437 |
{ |
{ |
438 |
|
CPUState *env; |
439 |
int nb_per_line, l, line_size, i, max_digits, len; |
int nb_per_line, l, line_size, i, max_digits, len; |
440 |
uint8_t buf[16]; |
uint8_t buf[16]; |
441 |
uint64_t v; |
uint64_t v; |
443 |
if (format == 'i') { |
if (format == 'i') { |
444 |
int flags; |
int flags; |
445 |
flags = 0; |
flags = 0; |
446 |
|
env = mon_get_cpu(); |
447 |
|
if (!env && !is_physical) |
448 |
|
return; |
449 |
#ifdef TARGET_I386 |
#ifdef TARGET_I386 |
450 |
if (wsize == 2) { |
if (wsize == 2) { |
451 |
flags = 1; |
flags = 1; |
452 |
} else if (wsize == 4) { |
} else if (wsize == 4) { |
453 |
flags = 0; |
flags = 0; |
454 |
} else { |
} else { |
455 |
/* as default we use the current CS size */ |
/* as default we use the current CS size */ |
456 |
flags = 0; |
flags = 0; |
457 |
if (!(cpu_single_env->segs[R_CS].flags & DESC_B_MASK)) |
if (env && !(env->segs[R_CS].flags & DESC_B_MASK)) |
458 |
flags = 1; |
flags = 1; |
459 |
} |
} |
460 |
#endif |
#endif |
461 |
monitor_disas(addr, count, is_physical, flags); |
monitor_disas(env, addr, count, is_physical, flags); |
462 |
return; |
return; |
463 |
} |
} |
464 |
|
|
495 |
if (is_physical) { |
if (is_physical) { |
496 |
cpu_physical_memory_rw(addr, buf, l, 0); |
cpu_physical_memory_rw(addr, buf, l, 0); |
497 |
} else { |
} else { |
498 |
cpu_memory_rw_debug(cpu_single_env, addr, buf, l, 0); |
env = mon_get_cpu(); |
499 |
|
if (!env) |
500 |
|
break; |
501 |
|
cpu_memory_rw_debug(env, addr, buf, l, 0); |
502 |
} |
} |
503 |
i = 0; |
i = 0; |
504 |
while (i < l) { |
while (i < l) { |
837 |
|
|
838 |
static void tlb_info(void) |
static void tlb_info(void) |
839 |
{ |
{ |
840 |
CPUState *env = cpu_single_env; |
CPUState *env; |
841 |
int l1, l2; |
int l1, l2; |
842 |
uint32_t pgd, pde, pte; |
uint32_t pgd, pde, pte; |
843 |
|
|
844 |
|
env = mon_get_cpu(); |
845 |
|
if (!env) |
846 |
|
return; |
847 |
|
|
848 |
if (!(env->cr[0] & CR0_PG_MASK)) { |
if (!(env->cr[0] & CR0_PG_MASK)) { |
849 |
term_printf("PG disabled\n"); |
term_printf("PG disabled\n"); |
850 |
return; |
return; |
895 |
|
|
896 |
static void mem_info(void) |
static void mem_info(void) |
897 |
{ |
{ |
898 |
CPUState *env = cpu_single_env; |
CPUState *env; |
899 |
int l1, l2, prot, last_prot; |
int l1, l2, prot, last_prot; |
900 |
uint32_t pgd, pde, pte, start, end; |
uint32_t pgd, pde, pte, start, end; |
901 |
|
|
902 |
|
env = mon_get_cpu(); |
903 |
|
if (!env) |
904 |
|
return; |
905 |
|
|
906 |
if (!(env->cr[0] & CR0_PG_MASK)) { |
if (!(env->cr[0] & CR0_PG_MASK)) { |
907 |
term_printf("PG disabled\n"); |
term_printf("PG disabled\n"); |
908 |
return; |
return; |
943 |
static void do_info_kqemu(void) |
static void do_info_kqemu(void) |
944 |
{ |
{ |
945 |
#ifdef USE_KQEMU |
#ifdef USE_KQEMU |
946 |
|
CPUState *env; |
947 |
int val; |
int val; |
948 |
val = 0; |
val = 0; |
949 |
if (cpu_single_env) |
env = mon_get_cpu(); |
950 |
val = cpu_single_env->kqemu_enabled; |
if (!env) { |
951 |
|
term_printf("No cpu initialized yet"); |
952 |
|
return; |
953 |
|
} |
954 |
|
val = env->kqemu_enabled; |
955 |
term_printf("kqemu is %s\n", val ? "enabled" : "disabled"); |
term_printf("kqemu is %s\n", val ? "enabled" : "disabled"); |
956 |
#else |
#else |
957 |
term_printf("kqemu support is not compiled\n"); |
term_printf("kqemu support is not compiled\n"); |
1008 |
"device", "add USB device (e.g. 'host:bus.addr' or 'host:vendor_id:product_id')" }, |
"device", "add USB device (e.g. 'host:bus.addr' or 'host:vendor_id:product_id')" }, |
1009 |
{ "usb_del", "s", do_usb_del, |
{ "usb_del", "s", do_usb_del, |
1010 |
"device", "remove USB device 'bus.addr'" }, |
"device", "remove USB device 'bus.addr'" }, |
1011 |
|
{ "cpu", "i", do_cpu_set, |
1012 |
|
"index", "set the default CPU" }, |
1013 |
{ NULL, NULL, }, |
{ NULL, NULL, }, |
1014 |
}; |
}; |
1015 |
|
|
1022 |
"", "show the block devices" }, |
"", "show the block devices" }, |
1023 |
{ "registers", "", do_info_registers, |
{ "registers", "", do_info_registers, |
1024 |
"", "show the cpu registers" }, |
"", "show the cpu registers" }, |
1025 |
|
{ "cpus", "", do_info_cpus, |
1026 |
|
"", "show infos for each CPU" }, |
1027 |
{ "history", "", do_info_history, |
{ "history", "", do_info_history, |
1028 |
"", "show the command line history", }, |
"", "show the command line history", }, |
1029 |
{ "irq", "", irq_info, |
{ "irq", "", irq_info, |
1067 |
#if defined(TARGET_I386) |
#if defined(TARGET_I386) |
1068 |
static target_long monitor_get_pc (struct MonitorDef *md, int val) |
static target_long monitor_get_pc (struct MonitorDef *md, int val) |
1069 |
{ |
{ |
1070 |
return cpu_single_env->eip + cpu_single_env->segs[R_CS].base; |
CPUState *env = mon_get_cpu(); |
1071 |
|
if (!env) |
1072 |
|
return 0; |
1073 |
|
return env->eip + env->segs[R_CS].base; |
1074 |
} |
} |
1075 |
#endif |
#endif |
1076 |
|
|
1077 |
#if defined(TARGET_PPC) |
#if defined(TARGET_PPC) |
1078 |
static target_long monitor_get_ccr (struct MonitorDef *md, int val) |
static target_long monitor_get_ccr (struct MonitorDef *md, int val) |
1079 |
{ |
{ |
1080 |
|
CPUState *env = mon_get_cpu(); |
1081 |
unsigned int u; |
unsigned int u; |
1082 |
int i; |
int i; |
1083 |
|
|
1084 |
|
if (!env) |
1085 |
|
return 0; |
1086 |
|
|
1087 |
u = 0; |
u = 0; |
1088 |
for (i = 0; i < 8; i++) |
for (i = 0; i < 8; i++) |
1089 |
u |= cpu_single_env->crf[i] << (32 - (4 * i)); |
u |= env->crf[i] << (32 - (4 * i)); |
1090 |
|
|
1091 |
return u; |
return u; |
1092 |
} |
} |
1093 |
|
|
1094 |
static target_long monitor_get_msr (struct MonitorDef *md, int val) |
static target_long monitor_get_msr (struct MonitorDef *md, int val) |
1095 |
{ |
{ |
1096 |
return (cpu_single_env->msr[MSR_POW] << MSR_POW) | |
CPUState *env = mon_get_cpu(); |
1097 |
(cpu_single_env->msr[MSR_ILE] << MSR_ILE) | |
if (!env) |
1098 |
(cpu_single_env->msr[MSR_EE] << MSR_EE) | |
return 0; |
1099 |
(cpu_single_env->msr[MSR_PR] << MSR_PR) | |
return (env->msr[MSR_POW] << MSR_POW) | |
1100 |
(cpu_single_env->msr[MSR_FP] << MSR_FP) | |
(env->msr[MSR_ILE] << MSR_ILE) | |
1101 |
(cpu_single_env->msr[MSR_ME] << MSR_ME) | |
(env->msr[MSR_EE] << MSR_EE) | |
1102 |
(cpu_single_env->msr[MSR_FE0] << MSR_FE0) | |
(env->msr[MSR_PR] << MSR_PR) | |
1103 |
(cpu_single_env->msr[MSR_SE] << MSR_SE) | |
(env->msr[MSR_FP] << MSR_FP) | |
1104 |
(cpu_single_env->msr[MSR_BE] << MSR_BE) | |
(env->msr[MSR_ME] << MSR_ME) | |
1105 |
(cpu_single_env->msr[MSR_FE1] << MSR_FE1) | |
(env->msr[MSR_FE0] << MSR_FE0) | |
1106 |
(cpu_single_env->msr[MSR_IP] << MSR_IP) | |
(env->msr[MSR_SE] << MSR_SE) | |
1107 |
(cpu_single_env->msr[MSR_IR] << MSR_IR) | |
(env->msr[MSR_BE] << MSR_BE) | |
1108 |
(cpu_single_env->msr[MSR_DR] << MSR_DR) | |
(env->msr[MSR_FE1] << MSR_FE1) | |
1109 |
(cpu_single_env->msr[MSR_RI] << MSR_RI) | |
(env->msr[MSR_IP] << MSR_IP) | |
1110 |
(cpu_single_env->msr[MSR_LE] << MSR_LE); |
(env->msr[MSR_IR] << MSR_IR) | |
1111 |
|
(env->msr[MSR_DR] << MSR_DR) | |
1112 |
|
(env->msr[MSR_RI] << MSR_RI) | |
1113 |
|
(env->msr[MSR_LE] << MSR_LE); |
1114 |
} |
} |
1115 |
|
|
1116 |
static target_long monitor_get_xer (struct MonitorDef *md, int val) |
static target_long monitor_get_xer (struct MonitorDef *md, int val) |
1117 |
{ |
{ |
1118 |
return (cpu_single_env->xer[XER_SO] << XER_SO) | |
CPUState *env = mon_get_cpu(); |
1119 |
(cpu_single_env->xer[XER_OV] << XER_OV) | |
if (!env) |
1120 |
(cpu_single_env->xer[XER_CA] << XER_CA) | |
return 0; |
1121 |
(cpu_single_env->xer[XER_BC] << XER_BC); |
return (env->xer[XER_SO] << XER_SO) | |
1122 |
|
(env->xer[XER_OV] << XER_OV) | |
1123 |
|
(env->xer[XER_CA] << XER_CA) | |
1124 |
|
(env->xer[XER_BC] << XER_BC); |
1125 |
} |
} |
1126 |
|
|
1127 |
static target_long monitor_get_decr (struct MonitorDef *md, int val) |
static target_long monitor_get_decr (struct MonitorDef *md, int val) |
1128 |
{ |
{ |
1129 |
return cpu_ppc_load_decr(cpu_single_env); |
CPUState *env = mon_get_cpu(); |
1130 |
|
if (!env) |
1131 |
|
return 0; |
1132 |
|
return cpu_ppc_load_decr(env); |
1133 |
} |
} |
1134 |
|
|
1135 |
static target_long monitor_get_tbu (struct MonitorDef *md, int val) |
static target_long monitor_get_tbu (struct MonitorDef *md, int val) |
1136 |
{ |
{ |
1137 |
return cpu_ppc_load_tbu(cpu_single_env); |
CPUState *env = mon_get_cpu(); |
1138 |
|
if (!env) |
1139 |
|
return 0; |
1140 |
|
return cpu_ppc_load_tbu(env); |
1141 |
} |
} |
1142 |
|
|
1143 |
static target_long monitor_get_tbl (struct MonitorDef *md, int val) |
static target_long monitor_get_tbl (struct MonitorDef *md, int val) |
1144 |
{ |
{ |
1145 |
return cpu_ppc_load_tbl(cpu_single_env); |
CPUState *env = mon_get_cpu(); |
1146 |
|
if (!env) |
1147 |
|
return 0; |
1148 |
|
return cpu_ppc_load_tbl(env); |
1149 |
} |
} |
1150 |
#endif |
#endif |
1151 |
|
|
1153 |
#ifndef TARGET_SPARC64 |
#ifndef TARGET_SPARC64 |
1154 |
static target_long monitor_get_psr (struct MonitorDef *md, int val) |
static target_long monitor_get_psr (struct MonitorDef *md, int val) |
1155 |
{ |
{ |
1156 |
return GET_PSR(cpu_single_env); |
CPUState *env = mon_get_cpu(); |
1157 |
|
if (!env) |
1158 |
|
return 0; |
1159 |
|
return GET_PSR(env); |
1160 |
} |
} |
1161 |
#endif |
#endif |
1162 |
|
|
1163 |
static target_long monitor_get_reg(struct MonitorDef *md, int val) |
static target_long monitor_get_reg(struct MonitorDef *md, int val) |
1164 |
{ |
{ |
1165 |
return cpu_single_env->regwptr[val]; |
CPUState *env = mon_get_cpu(); |
1166 |
|
if (!env) |
1167 |
|
return 0; |
1168 |
|
return env->regwptr[val]; |
1169 |
} |
} |
1170 |
#endif |
#endif |
1171 |
|
|
1375 |
longjmp(expr_env, 1); |
longjmp(expr_env, 1); |
1376 |
} |
} |
1377 |
|
|
1378 |
|
/* return 0 if OK, -1 if not found, -2 if no CPU defined */ |
1379 |
static int get_monitor_def(target_long *pval, const char *name) |
static int get_monitor_def(target_long *pval, const char *name) |
1380 |
{ |
{ |
1381 |
MonitorDef *md; |
MonitorDef *md; |
1386 |
if (md->get_value) { |
if (md->get_value) { |
1387 |
*pval = md->get_value(md, md->offset); |
*pval = md->get_value(md, md->offset); |
1388 |
} else { |
} else { |
1389 |
ptr = (uint8_t *)cpu_single_env + md->offset; |
CPUState *env = mon_get_cpu(); |
1390 |
|
if (!env) |
1391 |
|
return -2; |
1392 |
|
ptr = (uint8_t *)env + md->offset; |
1393 |
switch(md->type) { |
switch(md->type) { |
1394 |
case MD_I32: |
case MD_I32: |
1395 |
*pval = *(int32_t *)ptr; |
*pval = *(int32_t *)ptr; |
1423 |
{ |
{ |
1424 |
target_long n; |
target_long n; |
1425 |
char *p; |
char *p; |
1426 |
|
int ret; |
1427 |
|
|
1428 |
switch(*pch) { |
switch(*pch) { |
1429 |
case '+': |
case '+': |
1473 |
while (isspace(*pch)) |
while (isspace(*pch)) |
1474 |
pch++; |
pch++; |
1475 |
*q = 0; |
*q = 0; |
1476 |
if (get_monitor_def(&n, buf)) |
ret = get_monitor_def(&n, buf); |
1477 |
|
if (ret == -1) |
1478 |
expr_error("unknown register"); |
expr_error("unknown register"); |
1479 |
|
else if (ret == -2) |
1480 |
|
expr_error("no cpu defined"); |
1481 |
} |
} |
1482 |
break; |
break; |
1483 |
case '\0': |
case '\0': |