28 |
//#define DEBUG_VGA_MEM |
//#define DEBUG_VGA_MEM |
29 |
//#define DEBUG_VGA_REG |
//#define DEBUG_VGA_REG |
30 |
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//#define DEBUG_S3 |
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31 |
//#define DEBUG_BOCHS_VBE |
//#define DEBUG_BOCHS_VBE |
32 |
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/* S3 VGA is deprecated - another graphic card will be emulated */ |
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//#define CONFIG_S3VGA |
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33 |
/* force some bits to zero */ |
/* force some bits to zero */ |
34 |
const uint8_t sr_mask[8] = { |
const uint8_t sr_mask[8] = { |
35 |
(uint8_t)~0xfc, |
(uint8_t)~0xfc, |
221 |
#ifdef DEBUG_VGA_REG |
#ifdef DEBUG_VGA_REG |
222 |
printf("vga: read CR%x = 0x%02x\n", s->cr_index, val); |
printf("vga: read CR%x = 0x%02x\n", s->cr_index, val); |
223 |
#endif |
#endif |
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#ifdef DEBUG_S3 |
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if (s->cr_index >= 0x20) |
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printf("S3: CR read index=0x%x val=0x%x\n", |
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s->cr_index, val); |
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#endif |
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224 |
break; |
break; |
225 |
case 0x3ba: |
case 0x3ba: |
226 |
case 0x3da: |
case 0x3da: |
350 |
case 0x12: /* veritcal display end */ |
case 0x12: /* veritcal display end */ |
351 |
s->cr[s->cr_index] = val; |
s->cr[s->cr_index] = val; |
352 |
break; |
break; |
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#ifdef CONFIG_S3VGA |
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/* S3 registers */ |
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case 0x2d: |
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case 0x2e: |
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case 0x2f: |
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case 0x30: |
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/* chip ID, cannot write */ |
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break; |
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case 0x31: |
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/* update start address */ |
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{ |
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int v; |
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s->cr[s->cr_index] = val; |
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v = (val >> 4) & 3; |
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s->cr[0x69] = (s->cr[69] & ~0x03) | v; |
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} |
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break; |
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case 0x51: |
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/* update start address */ |
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{ |
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int v; |
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s->cr[s->cr_index] = val; |
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v = val & 3; |
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s->cr[0x69] = (s->cr[69] & ~0x0c) | (v << 2); |
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} |
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break; |
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#endif |
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353 |
default: |
default: |
354 |
s->cr[s->cr_index] = val; |
s->cr[s->cr_index] = val; |
355 |
break; |
break; |
356 |
} |
} |
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#ifdef DEBUG_S3 |
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if (s->cr_index >= 0x20) |
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printf("S3: CR write index=0x%x val=0x%x\n", |
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s->cr_index, val); |
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#endif |
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357 |
break; |
break; |
358 |
case 0x3ba: |
case 0x3ba: |
359 |
case 0x3da: |
case 0x3da: |
912 |
{ |
{ |
913 |
/* compute line_offset in bytes */ |
/* compute line_offset in bytes */ |
914 |
line_offset = s->cr[0x13]; |
line_offset = s->cr[0x13]; |
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#ifdef CONFIG_S3VGA |
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{ |
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uinr32_t v; |
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v = (s->cr[0x51] >> 4) & 3; /* S3 extension */ |
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if (v == 0) |
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v = (s->cr[0x43] >> 2) & 1; /* S3 extension */ |
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line_offset |= (v << 8); |
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} |
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#endif |
|
915 |
line_offset <<= 3; |
line_offset <<= 3; |
916 |
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917 |
/* starting address */ |
/* starting address */ |
918 |
start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8); |
start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8); |
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#ifdef CONFIG_S3VGA |
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start_addr |= (s->cr[0x69] & 0x1f) << 16; /* S3 extension */ |
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#endif |
|
919 |
} |
} |
920 |
*pline_offset = line_offset; |
*pline_offset = line_offset; |
921 |
*pstart_addr = start_addr; |
*pstart_addr = start_addr; |
1543 |
static void vga_reset(VGAState *s) |
static void vga_reset(VGAState *s) |
1544 |
{ |
{ |
1545 |
memset(s, 0, sizeof(VGAState)); |
memset(s, 0, sizeof(VGAState)); |
|
#ifdef CONFIG_S3VGA |
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/* chip ID for 8c968 */ |
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s->cr[0x2d] = 0x88; |
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s->cr[0x2e] = 0xb0; |
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s->cr[0x2f] = 0x01; /* XXX: check revision code */ |
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s->cr[0x30] = 0xe1; |
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#endif |
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1546 |
s->graphic_mode = -1; /* force full update */ |
s->graphic_mode = -1; /* force full update */ |
1547 |
} |
} |
1548 |
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