/[qemu]/qemu/hw/vga.c
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Diff of /qemu/hw/vga.c

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revision 1.39 by bellard, Thu Feb 10 22:00:27 2005 UTC revision 1.40 by bellard, Sat Apr 23 18:43:45 2005 UTC
# Line 28  Line 28 
28  //#define DEBUG_VGA_MEM  //#define DEBUG_VGA_MEM
29  //#define DEBUG_VGA_REG  //#define DEBUG_VGA_REG
30    
 //#define DEBUG_S3  
31  //#define DEBUG_BOCHS_VBE  //#define DEBUG_BOCHS_VBE
32    
 /* S3 VGA is deprecated - another graphic card will be emulated */  
 //#define CONFIG_S3VGA  
   
33  /* force some bits to zero */  /* force some bits to zero */
34  const uint8_t sr_mask[8] = {  const uint8_t sr_mask[8] = {
35      (uint8_t)~0xfc,      (uint8_t)~0xfc,
# Line 225  static uint32_t vga_ioport_read(void *op Line 221  static uint32_t vga_ioport_read(void *op
221  #ifdef DEBUG_VGA_REG  #ifdef DEBUG_VGA_REG
222              printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);              printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
223  #endif  #endif
 #ifdef DEBUG_S3  
             if (s->cr_index >= 0x20)  
                 printf("S3: CR read index=0x%x val=0x%x\n",  
                        s->cr_index, val);  
 #endif  
224              break;              break;
225          case 0x3ba:          case 0x3ba:
226          case 0x3da:          case 0x3da:
# Line 359  static void vga_ioport_write(void *opaqu Line 350  static void vga_ioport_write(void *opaqu
350          case 0x12: /* veritcal display end */          case 0x12: /* veritcal display end */
351              s->cr[s->cr_index] = val;              s->cr[s->cr_index] = val;
352              break;              break;
   
 #ifdef CONFIG_S3VGA  
             /* S3 registers */  
         case 0x2d:  
         case 0x2e:  
         case 0x2f:  
         case 0x30:  
             /* chip ID, cannot write */  
             break;  
         case 0x31:  
             /* update start address */  
             {  
                 int v;  
                 s->cr[s->cr_index] = val;  
                 v = (val >> 4) & 3;  
                 s->cr[0x69] = (s->cr[69] & ~0x03) | v;  
             }  
             break;  
         case 0x51:  
             /* update start address */  
             {  
                 int v;  
                 s->cr[s->cr_index] = val;  
                 v = val & 3;  
                 s->cr[0x69] = (s->cr[69] & ~0x0c) | (v << 2);  
             }  
             break;  
 #endif  
353          default:          default:
354              s->cr[s->cr_index] = val;              s->cr[s->cr_index] = val;
355              break;              break;
356          }          }
 #ifdef DEBUG_S3  
         if (s->cr_index >= 0x20)  
             printf("S3: CR write index=0x%x val=0x%x\n",  
                    s->cr_index, val);  
 #endif  
357          break;          break;
358      case 0x3ba:      case 0x3ba:
359      case 0x3da:      case 0x3da:
# Line 954  static void vga_get_offsets(VGAState *s, Line 912  static void vga_get_offsets(VGAState *s,
912      {        {  
913          /* compute line_offset in bytes */          /* compute line_offset in bytes */
914          line_offset = s->cr[0x13];          line_offset = s->cr[0x13];
 #ifdef CONFIG_S3VGA  
         {  
             uinr32_t v;  
             v = (s->cr[0x51] >> 4) & 3; /* S3 extension */  
             if (v == 0)  
                 v = (s->cr[0x43] >> 2) & 1; /* S3 extension */  
             line_offset |= (v << 8);  
         }  
 #endif  
915          line_offset <<= 3;          line_offset <<= 3;
916            
917          /* starting address */          /* starting address */
918          start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);          start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
 #ifdef CONFIG_S3VGA  
         start_addr |= (s->cr[0x69] & 0x1f) << 16; /* S3 extension */  
 #endif  
919      }      }
920      *pline_offset = line_offset;      *pline_offset = line_offset;
921      *pstart_addr = start_addr;      *pstart_addr = start_addr;
# Line 1597  void vga_invalidate_display(void) Line 1543  void vga_invalidate_display(void)
1543  static void vga_reset(VGAState *s)  static void vga_reset(VGAState *s)
1544  {  {
1545      memset(s, 0, sizeof(VGAState));      memset(s, 0, sizeof(VGAState));
 #ifdef CONFIG_S3VGA  
     /* chip ID for 8c968 */  
     s->cr[0x2d] = 0x88;  
     s->cr[0x2e] = 0xb0;  
     s->cr[0x2f] = 0x01; /* XXX: check revision code */  
     s->cr[0x30] = 0xe1;  
 #endif  
1546      s->graphic_mode = -1; /* force full update */      s->graphic_mode = -1; /* force full update */
1547  }  }
1548    

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