22 |
* THE SOFTWARE. |
* THE SOFTWARE. |
23 |
*/ |
*/ |
24 |
#include "vl.h" |
#include "vl.h" |
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#include "m48t08.h" |
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25 |
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26 |
#define KERNEL_LOAD_ADDR 0x00004000 |
#define KERNEL_LOAD_ADDR 0x00004000 |
27 |
#define CMDLINE_ADDR 0x007ff000 |
#define CMDLINE_ADDR 0x007ff000 |
87 |
{ |
{ |
88 |
} |
} |
89 |
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90 |
static void nvram_set_word (m48t08_t *nvram, uint32_t addr, uint16_t value) |
static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value) |
91 |
{ |
{ |
92 |
m48t08_write(nvram, addr++, (value >> 8) & 0xff); |
m48t59_write(nvram, addr++, (value >> 8) & 0xff); |
93 |
m48t08_write(nvram, addr++, value & 0xff); |
m48t59_write(nvram, addr++, value & 0xff); |
94 |
} |
} |
95 |
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96 |
static void nvram_set_lword (m48t08_t *nvram, uint32_t addr, uint32_t value) |
static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value) |
97 |
{ |
{ |
98 |
m48t08_write(nvram, addr++, value >> 24); |
m48t59_write(nvram, addr++, value >> 24); |
99 |
m48t08_write(nvram, addr++, (value >> 16) & 0xff); |
m48t59_write(nvram, addr++, (value >> 16) & 0xff); |
100 |
m48t08_write(nvram, addr++, (value >> 8) & 0xff); |
m48t59_write(nvram, addr++, (value >> 8) & 0xff); |
101 |
m48t08_write(nvram, addr++, value & 0xff); |
m48t59_write(nvram, addr++, value & 0xff); |
102 |
} |
} |
103 |
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104 |
static void nvram_set_string (m48t08_t *nvram, uint32_t addr, |
static void nvram_set_string (m48t59_t *nvram, uint32_t addr, |
105 |
const unsigned char *str, uint32_t max) |
const unsigned char *str, uint32_t max) |
106 |
{ |
{ |
107 |
unsigned int i; |
unsigned int i; |
108 |
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109 |
for (i = 0; i < max && str[i] != '\0'; i++) { |
for (i = 0; i < max && str[i] != '\0'; i++) { |
110 |
m48t08_write(nvram, addr + i, str[i]); |
m48t59_write(nvram, addr + i, str[i]); |
111 |
} |
} |
112 |
m48t08_write(nvram, addr + max - 1, '\0'); |
m48t59_write(nvram, addr + max - 1, '\0'); |
113 |
} |
} |
114 |
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115 |
static m48t08_t *nvram; |
static m48t59_t *nvram; |
116 |
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117 |
extern int nographic; |
extern int nographic; |
118 |
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119 |
static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline, |
static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
120 |
int boot_device, uint32_t RAM_size, |
int boot_device, uint32_t RAM_size, |
121 |
uint32_t kernel_size, |
uint32_t kernel_size, |
122 |
int width, int height, int depth) |
int width, int height, int depth) |
128 |
nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
129 |
nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */ |
nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */ |
130 |
// NVRAM_size, arch not applicable |
// NVRAM_size, arch not applicable |
131 |
m48t08_write(nvram, 0x2F, nographic & 0xff); |
m48t59_write(nvram, 0x2F, nographic & 0xff); |
132 |
nvram_set_lword(nvram, 0x30, RAM_size); |
nvram_set_lword(nvram, 0x30, RAM_size); |
133 |
m48t08_write(nvram, 0x34, boot_device & 0xff); |
m48t59_write(nvram, 0x34, boot_device & 0xff); |
134 |
nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR); |
nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR); |
135 |
nvram_set_lword(nvram, 0x3C, kernel_size); |
nvram_set_lword(nvram, 0x3C, kernel_size); |
136 |
if (cmdline) { |
if (cmdline) { |
145 |
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146 |
// Sun4m specific use |
// Sun4m specific use |
147 |
i = 0x1fd8; |
i = 0x1fd8; |
148 |
m48t08_write(nvram, i++, 0x01); |
m48t59_write(nvram, i++, 0x01); |
149 |
m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */ |
m48t59_write(nvram, i++, 0x80); /* Sun4m OBP */ |
150 |
j = 0; |
j = 0; |
151 |
m48t08_write(nvram, i++, macaddr[j++]); |
m48t59_write(nvram, i++, macaddr[j++]); |
152 |
m48t08_write(nvram, i++, macaddr[j++]); |
m48t59_write(nvram, i++, macaddr[j++]); |
153 |
m48t08_write(nvram, i++, macaddr[j++]); |
m48t59_write(nvram, i++, macaddr[j++]); |
154 |
m48t08_write(nvram, i++, macaddr[j++]); |
m48t59_write(nvram, i++, macaddr[j++]); |
155 |
m48t08_write(nvram, i++, macaddr[j++]); |
m48t59_write(nvram, i++, macaddr[j++]); |
156 |
m48t08_write(nvram, i, macaddr[j]); |
m48t59_write(nvram, i, macaddr[j]); |
157 |
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|
158 |
/* Calculate checksum */ |
/* Calculate checksum */ |
159 |
for (i = 0x1fd8; i < 0x1fe7; i++) { |
for (i = 0x1fd8; i < 0x1fe7; i++) { |
160 |
tmp ^= m48t08_read(nvram, i); |
tmp ^= m48t59_read(nvram, i); |
161 |
} |
} |
162 |
m48t08_write(nvram, 0x1fe7, tmp); |
m48t59_write(nvram, 0x1fe7, tmp); |
163 |
} |
} |
164 |
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165 |
static void *slavio_intctl; |
static void *slavio_intctl; |
230 |
slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G); |
slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G); |
231 |
tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height); |
tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height); |
232 |
lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA); |
lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA); |
233 |
nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE); |
nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8); |
234 |
slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ); |
slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ); |
235 |
slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ); |
slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ); |
236 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device |