36 |
// IRQs are not PIL ones, but master interrupt controller register |
// IRQs are not PIL ones, but master interrupt controller register |
37 |
// bits |
// bits |
38 |
#define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */ |
#define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */ |
39 |
#define PHYS_JJ_TCX_FB 0x50800000 /* Start address, frame buffer body */ |
#define PHYS_JJ_TCX_FB 0x50000000 /* TCX frame buffer */ |
40 |
|
#define PHYS_JJ_ESPDMA 0x78400000 /* ESP DMA controller */ |
41 |
|
#define PHYS_JJ_ESP 0x78800000 /* ESP SCSI */ |
42 |
|
#define PHYS_JJ_ESP_IRQ 18 |
43 |
#define PHYS_JJ_LEDMA 0x78400010 /* Lance DMA controller */ |
#define PHYS_JJ_LEDMA 0x78400010 /* Lance DMA controller */ |
44 |
#define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */ |
#define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */ |
45 |
#define PHYS_JJ_LE_IRQ 16 |
#define PHYS_JJ_LE_IRQ 16 |
53 |
#define PHYS_JJ_MS_KBD_IRQ 14 |
#define PHYS_JJ_MS_KBD_IRQ 14 |
54 |
#define PHYS_JJ_SER 0x71100000 /* Serial */ |
#define PHYS_JJ_SER 0x71100000 /* Serial */ |
55 |
#define PHYS_JJ_SER_IRQ 15 |
#define PHYS_JJ_SER_IRQ 15 |
|
#define PHYS_JJ_SCSI_IRQ 18 |
|
56 |
#define PHYS_JJ_FDC 0x71400000 /* Floppy */ |
#define PHYS_JJ_FDC 0x71400000 /* Floppy */ |
57 |
#define PHYS_JJ_FLOPPY_IRQ 22 |
#define PHYS_JJ_FLOPPY_IRQ 22 |
58 |
|
|
63 |
return qemu_get_clock(vm_clock); |
return qemu_get_clock(vm_clock); |
64 |
} |
} |
65 |
|
|
66 |
void DMA_run() {} |
int DMA_get_channel_mode (int nchan) |
67 |
|
{ |
68 |
|
return 0; |
69 |
|
} |
70 |
|
int DMA_read_memory (int nchan, void *buf, int pos, int size) |
71 |
|
{ |
72 |
|
return 0; |
73 |
|
} |
74 |
|
int DMA_write_memory (int nchan, void *buf, int pos, int size) |
75 |
|
{ |
76 |
|
return 0; |
77 |
|
} |
78 |
|
void DMA_hold_DREQ (int nchan) {} |
79 |
|
void DMA_release_DREQ (int nchan) {} |
80 |
|
void DMA_schedule(int nchan) {} |
81 |
|
void DMA_run (void) {} |
82 |
|
void DMA_init (int high_page_enable) {} |
83 |
|
void DMA_register_channel (int nchan, |
84 |
|
DMA_transfer_handler transfer_handler, |
85 |
|
void *opaque) |
86 |
|
{ |
87 |
|
} |
88 |
|
|
89 |
|
static void nvram_set_word (m48t08_t *nvram, uint32_t addr, uint16_t value) |
90 |
|
{ |
91 |
|
m48t08_write(nvram, addr++, (value >> 8) & 0xff); |
92 |
|
m48t08_write(nvram, addr++, value & 0xff); |
93 |
|
} |
94 |
|
|
95 |
|
static void nvram_set_lword (m48t08_t *nvram, uint32_t addr, uint32_t value) |
96 |
|
{ |
97 |
|
m48t08_write(nvram, addr++, value >> 24); |
98 |
|
m48t08_write(nvram, addr++, (value >> 16) & 0xff); |
99 |
|
m48t08_write(nvram, addr++, (value >> 8) & 0xff); |
100 |
|
m48t08_write(nvram, addr++, value & 0xff); |
101 |
|
} |
102 |
|
|
103 |
|
static void nvram_set_string (m48t08_t *nvram, uint32_t addr, |
104 |
|
const unsigned char *str, uint32_t max) |
105 |
|
{ |
106 |
|
unsigned int i; |
107 |
|
|
108 |
|
for (i = 0; i < max && str[i] != '\0'; i++) { |
109 |
|
m48t08_write(nvram, addr + i, str[i]); |
110 |
|
} |
111 |
|
m48t08_write(nvram, addr + max - 1, '\0'); |
112 |
|
} |
113 |
|
|
114 |
static m48t08_t *nvram; |
static m48t08_t *nvram; |
115 |
|
|
116 |
static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline) |
extern int nographic; |
117 |
|
|
118 |
|
static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline, |
119 |
|
int boot_device, uint32_t RAM_size, |
120 |
|
uint32_t kernel_size, |
121 |
|
int width, int height, int depth) |
122 |
{ |
{ |
123 |
unsigned char tmp = 0; |
unsigned char tmp = 0; |
124 |
int i, j; |
int i, j; |
125 |
|
|
126 |
i = 0x40; |
// Try to match PPC NVRAM |
127 |
|
nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
128 |
|
nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */ |
129 |
|
// NVRAM_size, arch not applicable |
130 |
|
m48t08_write(nvram, 0x2F, nographic & 0xff); |
131 |
|
nvram_set_lword(nvram, 0x30, RAM_size); |
132 |
|
m48t08_write(nvram, 0x34, boot_device & 0xff); |
133 |
|
nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR); |
134 |
|
nvram_set_lword(nvram, 0x3C, kernel_size); |
135 |
if (cmdline) { |
if (cmdline) { |
|
uint32_t cmdline_len; |
|
|
|
|
136 |
strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
137 |
m48t08_write(nvram, i++, CMDLINE_ADDR >> 24); |
nvram_set_lword(nvram, 0x40, CMDLINE_ADDR); |
138 |
m48t08_write(nvram, i++, (CMDLINE_ADDR >> 16) & 0xff); |
nvram_set_lword(nvram, 0x44, strlen(cmdline)); |
|
m48t08_write(nvram, i++, (CMDLINE_ADDR >> 8) & 0xff); |
|
|
m48t08_write(nvram, i++, CMDLINE_ADDR & 0xff); |
|
|
|
|
|
cmdline_len = strlen(cmdline); |
|
|
m48t08_write(nvram, i++, cmdline_len >> 24); |
|
|
m48t08_write(nvram, i++, (cmdline_len >> 16) & 0xff); |
|
|
m48t08_write(nvram, i++, (cmdline_len >> 8) & 0xff); |
|
|
m48t08_write(nvram, i++, cmdline_len & 0xff); |
|
139 |
} |
} |
140 |
|
// initrd_image, initrd_size passed differently |
141 |
|
nvram_set_word(nvram, 0x54, width); |
142 |
|
nvram_set_word(nvram, 0x56, height); |
143 |
|
nvram_set_word(nvram, 0x58, depth); |
144 |
|
|
145 |
|
// Sun4m specific use |
146 |
i = 0x1fd8; |
i = 0x1fd8; |
147 |
m48t08_write(nvram, i++, 0x01); |
m48t08_write(nvram, i++, 0x01); |
148 |
m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */ |
m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */ |
211 |
char buf[1024]; |
char buf[1024]; |
212 |
int ret, linux_boot; |
int ret, linux_boot; |
213 |
unsigned int i; |
unsigned int i; |
214 |
unsigned long vram_size = 0x100000, prom_offset, initrd_size; |
long vram_size = 0x100000, prom_offset, initrd_size, kernel_size; |
215 |
|
|
216 |
linux_boot = (kernel_filename != NULL); |
linux_boot = (kernel_filename != NULL); |
217 |
|
|
220 |
|
|
221 |
iommu = iommu_init(PHYS_JJ_IOMMU); |
iommu = iommu_init(PHYS_JJ_IOMMU); |
222 |
slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G); |
slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G); |
223 |
tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size); |
tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height); |
224 |
lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA); |
lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA); |
225 |
nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE); |
nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE); |
|
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline); |
|
226 |
slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ); |
slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ); |
227 |
slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ); |
slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ); |
228 |
slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[0], serial_hds[1]); |
slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[0], serial_hds[1]); |
229 |
fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table); |
fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table); |
230 |
|
esp_init(bs_table, PHYS_JJ_ESP_IRQ, PHYS_JJ_ESP, PHYS_JJ_ESPDMA); |
231 |
|
|
232 |
prom_offset = ram_size + vram_size; |
prom_offset = ram_size + vram_size; |
233 |
|
|
245 |
cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, |
cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, |
246 |
prom_offset | IO_MEM_ROM); |
prom_offset | IO_MEM_ROM); |
247 |
|
|
248 |
|
kernel_size = 0; |
249 |
if (linux_boot) { |
if (linux_boot) { |
250 |
ret = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
kernel_size = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
251 |
if (ret < 0) |
if (kernel_size < 0) |
252 |
ret = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
253 |
if (ret < 0) |
if (kernel_size < 0) |
254 |
ret = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
255 |
if (ret < 0) { |
if (kernel_size < 0) { |
256 |
fprintf(stderr, "qemu: could not load kernel '%s'\n", |
fprintf(stderr, "qemu: could not load kernel '%s'\n", |
257 |
kernel_filename); |
kernel_filename); |
258 |
exit(1); |
exit(1); |
279 |
} |
} |
280 |
} |
} |
281 |
} |
} |
282 |
|
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth); |
283 |
} |
} |