/[qemu]/qemu/hw/sun4m.c
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Diff of /qemu/hw/sun4m.c

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revision 1.2 by bellard, Mon Oct 4 21:23:09 2004 UTC revision 1.3 by bellard, Sun Dec 19 23:18:01 2004 UTC
# Line 25  Line 25 
25  #include "m48t08.h"  #include "m48t08.h"
26    
27  #define KERNEL_LOAD_ADDR     0x00004000  #define KERNEL_LOAD_ADDR     0x00004000
28  #define MMU_CONTEXT_TBL      0x00003000  #define PROM_ADDR            0xffd00000
 #define MMU_L1PTP            (MMU_CONTEXT_TBL + 0x0400)  
 #define MMU_L2PTP            (MMU_CONTEXT_TBL + 0x0800)  
 #define PROM_ADDR            0xffd04000  
29  #define PROM_FILENAMEB       "proll.bin"  #define PROM_FILENAMEB       "proll.bin"
30  #define PROM_FILENAMEE       "proll.elf"  #define PROM_FILENAMEE       "proll.elf"
31  #define PROLL_MAGIC_ADDR 0x20000000  #define PHYS_JJ_EEPROM  0x71200000      /* m48t08 */
 #define PHYS_JJ_EEPROM  0x71200000      /* [2000] MK48T08 */  
32  #define PHYS_JJ_IDPROM_OFF      0x1FD8  #define PHYS_JJ_IDPROM_OFF      0x1FD8
33  #define PHYS_JJ_EEPROM_SIZE     0x2000  #define PHYS_JJ_EEPROM_SIZE     0x2000
34  #define PHYS_JJ_IOMMU   0x10000000      /* First page of sun4m IOMMU */  // IRQs are not PIL ones, but master interrupt controller register
35    // bits
36    #define PHYS_JJ_IOMMU   0x10000000      /* I/O MMU */
37  #define PHYS_JJ_TCX_FB  0x50800000      /* Start address, frame buffer body */  #define PHYS_JJ_TCX_FB  0x50800000      /* Start address, frame buffer body */
38  #define PHYS_JJ_TCX_0E  0x5E000000      /* Top address, one byte used. */  #define PHYS_JJ_LEDMA   0x78400010      /* Lance DMA controller */
39  #define PHYS_JJ_IOMMU   0x10000000      /* First page of sun4m IOMMU */  #define PHYS_JJ_LE      0x78C00000      /* Lance ethernet */
40  #define PHYS_JJ_LEDMA   0x78400010      /* ledma, off by 10 from unused SCSI */  #define PHYS_JJ_LE_IRQ     16
41  #define PHYS_JJ_LE      0x78C00000      /* LANCE, typical sun4m */  #define PHYS_JJ_CLOCK   0x71D00000      /* Per-CPU timer/counter, L14 */
42  #define PHYS_JJ_LE_IRQ  6  #define PHYS_JJ_CLOCK_IRQ  7
43  #define PHYS_JJ_CLOCK   0x71D00000  #define PHYS_JJ_CLOCK1  0x71D10000      /* System timer/counter, L10 */
44  #define PHYS_JJ_CLOCK_IRQ  10  #define PHYS_JJ_CLOCK1_IRQ 19
45  #define PHYS_JJ_CLOCK1  0x71D10000  #define PHYS_JJ_INTR0   0x71E00000      /* Per-CPU interrupt control registers */
 #define PHYS_JJ_CLOCK1_IRQ  14  
 #define PHYS_JJ_INTR0   0x71E00000      /* CPU0 interrupt control registers */  
46  #define PHYS_JJ_INTR_G  0x71E10000      /* Master interrupt control registers */  #define PHYS_JJ_INTR_G  0x71E10000      /* Master interrupt control registers */
47    #define PHYS_JJ_MS_KBD  0x71000000      /* Mouse and keyboard */
48    #define PHYS_JJ_MS_KBD_IRQ    14
49    #define PHYS_JJ_SER     0x71100000      /* Serial */
50    #define PHYS_JJ_SER_IRQ    15
51    #define PHYS_JJ_SCSI_IRQ   18
52    #define PHYS_JJ_FDC     0x71400000      /* Floppy */
53    #define PHYS_JJ_FLOPPY_IRQ 22
54    
55  /* TSC handling */  /* TSC handling */
56    
# Line 57  uint64_t cpu_get_tsc() Line 60  uint64_t cpu_get_tsc()
60  }  }
61    
62  void DMA_run() {}  void DMA_run() {}
 void SB16_run() {}  
 int serial_can_receive(SerialState *s) { return 0; }  
 void serial_receive_byte(SerialState *s, int ch) {}  
 void serial_receive_break(SerialState *s) {}  
63    
64  static m48t08_t *nvram;  static m48t08_t *nvram;
65    
66    static void nvram_init(m48t08_t *nvram, uint8_t *macaddr)
67    {
68        unsigned char tmp = 0;
69        int i, j;
70    
71        i = 0x1fd8;
72        m48t08_write(nvram, i++, 0x01);
73        m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */
74        j = 0;
75        m48t08_write(nvram, i++, macaddr[j++]);
76        m48t08_write(nvram, i++, macaddr[j++]);
77        m48t08_write(nvram, i++, macaddr[j++]);
78        m48t08_write(nvram, i++, macaddr[j++]);
79        m48t08_write(nvram, i++, macaddr[j++]);
80        m48t08_write(nvram, i, macaddr[j]);
81    
82        /* Calculate checksum */
83        for (i = 0x1fd8; i < 0x1fe7; i++) {
84            tmp ^= m48t08_read(nvram, i);
85        }
86        m48t08_write(nvram, 0x1fe7, tmp);
87    }
88    
89    static void *slavio_intctl;
90    
91    void pic_info()
92    {
93        slavio_pic_info(slavio_intctl);
94    }
95    
96    void irq_info()
97    {
98        slavio_irq_info(slavio_intctl);
99    }
100    
101    void pic_set_irq(int irq, int level)
102    {
103        slavio_pic_set_irq(slavio_intctl, irq, level);
104    }
105    
106    static void *tcx;
107    
108    void vga_update_display()
109    {
110        tcx_update_display(tcx);
111    }
112    
113    void vga_invalidate_display()
114    {
115        tcx_invalidate_display(tcx);
116    }
117    
118    void vga_screen_dump(const char *filename)
119    {
120        tcx_screen_dump(tcx, filename);
121    }
122    
123    static void *iommu;
124    
125    uint32_t iommu_translate(uint32_t addr)
126    {
127        return iommu_translate_local(iommu, addr);
128    }
129    
130  /* Sun4m hardware initialisation */  /* Sun4m hardware initialisation */
131  void sun4m_init(int ram_size, int vga_ram_size, int boot_device,  void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
132               DisplayState *ds, const char **fd_filename, int snapshot,               DisplayState *ds, const char **fd_filename, int snapshot,
# Line 72  void sun4m_init(int ram_size, int vga_ra Line 135  void sun4m_init(int ram_size, int vga_ra
135  {  {
136      char buf[1024];      char buf[1024];
137      int ret, linux_boot;      int ret, linux_boot;
138      unsigned long bios_offset;      unsigned long vram_size = 0x100000, prom_offset;
139    
140      linux_boot = (kernel_filename != NULL);      linux_boot = (kernel_filename != NULL);
141    
142      /* allocate RAM */      /* allocate RAM */
143      cpu_register_physical_memory(0, ram_size, 0);      cpu_register_physical_memory(0, ram_size, 0);
     bios_offset = ram_size;  
144    
145      iommu_init(PHYS_JJ_IOMMU);      iommu = iommu_init(PHYS_JJ_IOMMU);
146      sched_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);      slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
147      tcx_init(ds, PHYS_JJ_TCX_FB);      tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size);
148      lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);      lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
149      nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE, &nd_table[0].macaddr);      nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE);
150      timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ);      nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr);
151      timer_init(PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ);      slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ);
152      magic_init(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR, PROLL_MAGIC_ADDR);      slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ);
153        slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[0], serial_hds[1]);
154        fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table);
155    
156        prom_offset = ram_size + vram_size;
157    
158        snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE);
159        ret = load_elf(buf, phys_ram_base + prom_offset);
160        if (ret < 0) {
161            snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB);
162            ret = load_image(buf, phys_ram_base + prom_offset);
163        }
164        if (ret < 0) {
165            fprintf(stderr, "qemu: could not load prom '%s'\n",
166                    buf);
167            exit(1);
168        }
169        cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
170                                     prom_offset | IO_MEM_ROM);
171    
     /* We load Proll as the kernel and start it. It will issue a magic  
        IO to load the real kernel */  
172      if (linux_boot) {      if (linux_boot) {
173          snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB);          ret = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
174          ret = load_kernel(buf,          if (ret < 0)
175                         phys_ram_base + KERNEL_LOAD_ADDR);              ret = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
176            if (ret < 0)
177                ret = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
178          if (ret < 0) {          if (ret < 0) {
179              fprintf(stderr, "qemu: could not load kernel '%s'\n",              fprintf(stderr, "qemu: could not load kernel '%s'\n",
180                      buf);                      kernel_filename);
181              exit(1);              exit(1);
182          }          }
183      }      }
     /* Setup a MMU entry for entire address space */  
     stl_raw(phys_ram_base + MMU_CONTEXT_TBL, (MMU_L1PTP >> 4) | 1);  
     stl_raw(phys_ram_base + MMU_L1PTP, (MMU_L2PTP >> 4) | 1);  
     stl_raw(phys_ram_base + MMU_L1PTP + (0x01 << 2), (MMU_L2PTP >> 4) | 1); // 01.. == 00..  
     stl_raw(phys_ram_base + MMU_L1PTP + (0xff << 2), (MMU_L2PTP >> 4) | 1); // ff.. == 00..  
     stl_raw(phys_ram_base + MMU_L1PTP + (0xf0 << 2), (MMU_L2PTP >> 4) | 1); // f0.. == 00..  
     /* 3 = U:RWX S:RWX */  
     stl_raw(phys_ram_base + MMU_L2PTP, (3 << PTE_ACCESS_SHIFT) | 2);  
     stl_raw(phys_ram_base + MMU_L2PTP, ((0x01 << PTE_PPN_SHIFT) >> 4 ) | (3 << PTE_ACCESS_SHIFT) | 2);  
184  }  }

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