96 |
return 0; |
return 0; |
97 |
} |
} |
98 |
|
|
99 |
|
static void pic_irq_request(void *opaque, int level) |
100 |
|
{ |
101 |
|
if (level) |
102 |
|
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); |
103 |
|
else |
104 |
|
cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); |
105 |
|
} |
106 |
|
|
107 |
/* PCI intack register */ |
/* PCI intack register */ |
108 |
/* Read-only register (?) */ |
/* Read-only register (?) */ |
109 |
static void _PPC_intack_write (void *opaque, target_phys_addr_t addr, uint32_t value) |
static void _PPC_intack_write (void *opaque, target_phys_addr_t addr, uint32_t value) |
116 |
uint32_t retval = 0; |
uint32_t retval = 0; |
117 |
|
|
118 |
if (addr == 0xBFFFFFF0) |
if (addr == 0xBFFFFFF0) |
119 |
retval = pic_intack_read(NULL); |
retval = pic_intack_read(isa_pic); |
120 |
// printf("%s: 0x%08x <= %d\n", __func__, addr, retval); |
// printf("%s: 0x%08x <= %d\n", __func__, addr, retval); |
121 |
|
|
122 |
return retval; |
return retval; |
513 |
&PPC_prep_io_readl, |
&PPC_prep_io_readl, |
514 |
}; |
}; |
515 |
|
|
|
extern CPUPPCState *global_env; |
|
|
|
|
516 |
#define NVRAM_SIZE 0x2000 |
#define NVRAM_SIZE 0x2000 |
517 |
|
|
518 |
/* PowerPC PREP hardware initialisation */ |
/* PowerPC PREP hardware initialisation */ |
599 |
vga_ram_size); |
vga_ram_size); |
600 |
rtc_init(0x70, 8); |
rtc_init(0x70, 8); |
601 |
// openpic = openpic_init(0x00000000, 0xF0000000, 1); |
// openpic = openpic_init(0x00000000, 0xF0000000, 1); |
602 |
// pic_init(openpic); |
isa_pic = pic_init(pic_irq_request, cpu_single_env); |
|
pic_init(); |
|
603 |
// pit = pit_init(0x40, 0); |
// pit = pit_init(0x40, 0); |
604 |
|
|
605 |
serial_init(0x3f8, 4, serial_hds[0]); |
serial_init(0x3f8, 4, serial_hds[0]); |