/[qemu]/qemu/hw/ppc_chrp.c
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Diff of /qemu/hw/ppc_chrp.c

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revision 1.15 by bellard, Sun Jul 3 16:00:32 2005 UTC revision 1.16 by bellard, Thu Jul 7 21:47:27 2005 UTC
# Line 31  Line 31 
31  #define INITRD_LOAD_ADDR 0x01800000  #define INITRD_LOAD_ADDR 0x01800000
32    
33  /* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,  /* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
34     NVRAM (not implemented).  */     NVRAM */
35    
36  static int dbdma_mem_index;  static int dbdma_mem_index;
37  static int cuda_mem_index;  static int cuda_mem_index;
# Line 39  static int ide0_mem_index = -1; Line 39  static int ide0_mem_index = -1;
39  static int ide1_mem_index = -1;  static int ide1_mem_index = -1;
40  static int openpic_mem_index = -1;  static int openpic_mem_index = -1;
41  static int heathrow_pic_mem_index = -1;  static int heathrow_pic_mem_index = -1;
42    static int macio_nvram_mem_index = -1;
43    
44  /* DBDMA: currently no op - should suffice right now */  /* DBDMA: currently no op - should suffice right now */
45    
# Line 83  static CPUReadMemoryFunc *dbdma_read[] = Line 84  static CPUReadMemoryFunc *dbdma_read[] =
84      &dbdma_readl,      &dbdma_readl,
85  };  };
86    
87    /* macio style NVRAM device */
88    typedef struct MacIONVRAMState {
89        uint8_t data[0x2000];
90    } MacIONVRAMState;
91    
92    static void macio_nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
93    {
94        MacIONVRAMState *s = opaque;
95        addr = (addr >> 4) & 0x1fff;
96        s->data[addr] = value;
97        //    printf("macio_nvram_writeb %04x = %02x\n", addr, value);
98    }
99    
100    static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
101    {
102        MacIONVRAMState *s = opaque;
103        uint32_t value;
104    
105        addr = (addr >> 4) & 0x1fff;
106        value = s->data[addr];
107        //    printf("macio_nvram_readb %04x = %02x\n", addr, value);
108        return value;
109    }
110    
111    static CPUWriteMemoryFunc *macio_nvram_write[] = {
112        &macio_nvram_writeb,
113        &macio_nvram_writeb,
114        &macio_nvram_writeb,
115    };
116    
117    static CPUReadMemoryFunc *macio_nvram_read[] = {
118        &macio_nvram_readb,
119        &macio_nvram_readb,
120        &macio_nvram_readb,
121    };
122    
123    static MacIONVRAMState *macio_nvram_init(void)
124    {
125        MacIONVRAMState *s;
126        s = qemu_mallocz(sizeof(MacIONVRAMState));
127        if (!s)
128            return NULL;
129        macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read,
130                                                       macio_nvram_write, s);
131        return s;
132    }
133    
134  static void macio_map(PCIDevice *pci_dev, int region_num,  static void macio_map(PCIDevice *pci_dev, int region_num,
135                        uint32_t addr, uint32_t size, int type)                        uint32_t addr, uint32_t size, int type)
136  {  {
# Line 100  static void macio_map(PCIDevice *pci_dev Line 148  static void macio_map(PCIDevice *pci_dev
148          cpu_register_physical_memory(addr + 0x40000, 0x40000,          cpu_register_physical_memory(addr + 0x40000, 0x40000,
149                                       openpic_mem_index);                                       openpic_mem_index);
150      }      }
151        if (macio_nvram_mem_index >= 0)
152            cpu_register_physical_memory(addr + 0x60000, 0x20000, macio_nvram_mem_index);
153  }  }
154    
155  static void macio_init(PCIBus *bus)  static void macio_init(PCIBus *bus, int device_id)
156  {  {
157      PCIDevice *d;      PCIDevice *d;
158    
# Line 112  static void macio_init(PCIBus *bus) Line 162  static void macio_init(PCIBus *bus)
162         in PearPC */         in PearPC */
163      d->config[0x00] = 0x6b; // vendor_id      d->config[0x00] = 0x6b; // vendor_id
164      d->config[0x01] = 0x10;      d->config[0x01] = 0x10;
165      d->config[0x02] = 0x22;      d->config[0x02] = device_id;
166      d->config[0x03] = 0x00;      d->config[0x03] = device_id >> 8;
167    
168      d->config[0x0a] = 0x00; // class_sub = pci2pci      d->config[0x0a] = 0x00; // class_sub = pci2pci
169      d->config[0x0b] = 0xff; // class_base = bridge      d->config[0x0b] = 0xff; // class_base = bridge
# Line 219  static void pic_irq_request(void *opaque Line 269  static void pic_irq_request(void *opaque
269  {  {
270  }  }
271    
272    static uint8_t nvram_chksum(const uint8_t *buf, int n)
273    {
274        int sum, i;
275        sum = 0;
276        for(i = 0; i < n; i++)
277            sum += buf[i];
278        return (sum & 0xff) + (sum >> 8);
279    }
280    
281    /* set a free Mac OS NVRAM partition */
282    void pmac_format_nvram_partition(uint8_t *buf, int len)
283    {
284        char partition_name[12] = "wwwwwwwwwwww";
285        
286        buf[0] = 0x7f; /* free partition magic */
287        buf[1] = 0; /* checksum */
288        buf[2] = len >> 8;
289        buf[3] = len;
290        memcpy(buf + 4, partition_name, 12);
291        buf[1] = nvram_chksum(buf, 16);
292    }    
293    
294  /* PowerPC CHRP hardware initialisation */  /* PowerPC CHRP hardware initialisation */
295  static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,  static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
296                            DisplayState *ds, const char **fd_filename,                            DisplayState *ds, const char **fd_filename,
# Line 369  static void ppc_chrp_init(int ram_size, Line 441  static void ppc_chrp_init(int ram_size,
441          adb_kbd_init(&adb_bus);          adb_kbd_init(&adb_bus);
442          adb_mouse_init(&adb_bus);          adb_mouse_init(&adb_bus);
443                    
444          macio_init(pci_bus);          {
445                MacIONVRAMState *nvr;
446                nvr = macio_nvram_init();
447                pmac_format_nvram_partition(nvr->data, 0x2000);
448            }
449    
450            macio_init(pci_bus, 0x0017);
451                    
452          nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);          nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
453                    
# Line 416  static void ppc_chrp_init(int ram_size, Line 494  static void ppc_chrp_init(int ram_size,
494          adb_kbd_init(&adb_bus);          adb_kbd_init(&adb_bus);
495          adb_mouse_init(&adb_bus);          adb_mouse_init(&adb_bus);
496                    
497          macio_init(pci_bus);          macio_init(pci_bus, 0x0022);
498                    
499          nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);          nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
500                    

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