45 |
int devfn_min; |
int devfn_min; |
46 |
void (*set_irq)(PCIDevice *pci_dev, int irq_num, int level); |
void (*set_irq)(PCIDevice *pci_dev, int irq_num, int level); |
47 |
uint32_t config_reg; /* XXX: suppress */ |
uint32_t config_reg; /* XXX: suppress */ |
48 |
openpic_t *openpic; /* XXX: suppress */ |
/* low level pic */ |
49 |
|
SetIRQFunc *low_set_irq; |
50 |
|
void *irq_opaque; |
51 |
PCIDevice *devices[256]; |
PCIDevice *devices[256]; |
52 |
}; |
}; |
53 |
|
|
725 |
PPC_PCIIO_write, s); |
PPC_PCIIO_write, s); |
726 |
cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory); |
cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory); |
727 |
|
|
728 |
d = pci_register_device(s, "PREP PCI Bridge", sizeof(PCIDevice), 0, |
/* PCI host bridge */ |
729 |
NULL, NULL); |
d = pci_register_device(s, "PREP Host Bridge - Motorola Raven", |
730 |
|
sizeof(PCIDevice), 0, NULL, NULL); |
731 |
/* XXX: put correct IDs */ |
d->config[0x00] = 0x57; // vendor_id : Motorola |
|
d->config[0x00] = 0x11; // vendor_id |
|
732 |
d->config[0x01] = 0x10; |
d->config[0x01] = 0x10; |
733 |
d->config[0x02] = 0x26; // device_id |
d->config[0x02] = 0x01; // device_id : Raven |
734 |
d->config[0x03] = 0x00; |
d->config[0x03] = 0x48; |
735 |
d->config[0x08] = 0x02; // revision |
d->config[0x08] = 0x00; // revision |
736 |
d->config[0x0a] = 0x04; // class_sub = pci2pci |
d->config[0x0A] = 0x00; // class_sub = pci host |
737 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
d->config[0x0B] = 0x06; // class_base = PCI_bridge |
738 |
d->config[0x0e] = 0x01; // header_type |
d->config[0x0C] = 0x08; // cache_line_size |
739 |
|
d->config[0x0D] = 0x10; // latency_timer |
740 |
|
d->config[0x0E] = 0x00; // header_type |
741 |
|
d->config[0x34] = 0x00; // capabilities_pointer |
742 |
|
|
743 |
return s; |
return s; |
744 |
} |
} |
745 |
|
|
746 |
|
|
|
/* pmac pci init */ |
|
|
|
|
|
#if 0 |
|
747 |
/* Grackle PCI host */ |
/* Grackle PCI host */ |
748 |
static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr, |
static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr, |
749 |
uint32_t val) |
uint32_t val) |
848 |
&pci_grackle_readw, |
&pci_grackle_readw, |
849 |
&pci_grackle_readl, |
&pci_grackle_readl, |
850 |
}; |
}; |
851 |
|
|
852 |
|
void pci_set_pic(PCIBus *bus, SetIRQFunc *set_irq, void *irq_opaque) |
853 |
|
{ |
854 |
|
bus->low_set_irq = set_irq; |
855 |
|
bus->irq_opaque = irq_opaque; |
856 |
|
} |
857 |
|
|
858 |
|
/* XXX: we do not simulate the hardware - we rely on the BIOS to |
859 |
|
set correctly for irq line field */ |
860 |
|
static void pci_set_irq_simple(PCIDevice *d, int irq_num, int level) |
861 |
|
{ |
862 |
|
PCIBus *s = d->bus; |
863 |
|
s->low_set_irq(s->irq_opaque, d->config[PCI_INTERRUPT_LINE], level); |
864 |
|
} |
865 |
|
|
866 |
|
PCIBus *pci_grackle_init(uint32_t base) |
867 |
|
{ |
868 |
|
PCIBus *s; |
869 |
|
PCIDevice *d; |
870 |
|
int pci_mem_config, pci_mem_data; |
871 |
|
|
872 |
|
s = pci_register_bus(); |
873 |
|
s->set_irq = pci_set_irq_simple; |
874 |
|
|
875 |
|
pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read, |
876 |
|
pci_grackle_config_write, s); |
877 |
|
pci_mem_data = cpu_register_io_memory(0, pci_grackle_read, |
878 |
|
pci_grackle_write, s); |
879 |
|
cpu_register_physical_memory(base, 0x1000, pci_mem_config); |
880 |
|
cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data); |
881 |
|
d = pci_register_device(s, "Grackle host bridge", sizeof(PCIDevice), |
882 |
|
0, NULL, NULL); |
883 |
|
d->config[0x00] = 0x57; // vendor_id |
884 |
|
d->config[0x01] = 0x10; |
885 |
|
d->config[0x02] = 0x02; // device_id |
886 |
|
d->config[0x03] = 0x00; |
887 |
|
d->config[0x08] = 0x00; // revision |
888 |
|
d->config[0x09] = 0x01; |
889 |
|
d->config[0x0a] = 0x00; // class_sub = host |
890 |
|
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
891 |
|
d->config[0x0e] = 0x00; // header_type |
892 |
|
|
893 |
|
d->config[0x18] = 0x00; // primary_bus |
894 |
|
d->config[0x19] = 0x01; // secondary_bus |
895 |
|
d->config[0x1a] = 0x00; // subordinate_bus |
896 |
|
d->config[0x1c] = 0x00; |
897 |
|
d->config[0x1d] = 0x00; |
898 |
|
|
899 |
|
d->config[0x20] = 0x00; // memory_base |
900 |
|
d->config[0x21] = 0x00; |
901 |
|
d->config[0x22] = 0x01; // memory_limit |
902 |
|
d->config[0x23] = 0x00; |
903 |
|
|
904 |
|
d->config[0x24] = 0x00; // prefetchable_memory_base |
905 |
|
d->config[0x25] = 0x00; |
906 |
|
d->config[0x26] = 0x00; // prefetchable_memory_limit |
907 |
|
d->config[0x27] = 0x00; |
908 |
|
|
909 |
|
#if 0 |
910 |
|
/* PCI2PCI bridge same values as PearPC - check this */ |
911 |
|
d->config[0x00] = 0x11; // vendor_id |
912 |
|
d->config[0x01] = 0x10; |
913 |
|
d->config[0x02] = 0x26; // device_id |
914 |
|
d->config[0x03] = 0x00; |
915 |
|
d->config[0x08] = 0x02; // revision |
916 |
|
d->config[0x0a] = 0x04; // class_sub = pci2pci |
917 |
|
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
918 |
|
d->config[0x0e] = 0x01; // header_type |
919 |
|
|
920 |
|
d->config[0x18] = 0x0; // primary_bus |
921 |
|
d->config[0x19] = 0x1; // secondary_bus |
922 |
|
d->config[0x1a] = 0x1; // subordinate_bus |
923 |
|
d->config[0x1c] = 0x10; // io_base |
924 |
|
d->config[0x1d] = 0x20; // io_limit |
925 |
|
|
926 |
|
d->config[0x20] = 0x80; // memory_base |
927 |
|
d->config[0x21] = 0x80; |
928 |
|
d->config[0x22] = 0x90; // memory_limit |
929 |
|
d->config[0x23] = 0x80; |
930 |
|
|
931 |
|
d->config[0x24] = 0x00; // prefetchable_memory_base |
932 |
|
d->config[0x25] = 0x84; |
933 |
|
d->config[0x26] = 0x00; // prefetchable_memory_limit |
934 |
|
d->config[0x27] = 0x85; |
935 |
#endif |
#endif |
936 |
|
return s; |
937 |
|
} |
938 |
|
|
939 |
/* Uninorth PCI host (for all Mac99 and newer machines */ |
/* Uninorth PCI host (for all Mac99 and newer machines */ |
940 |
static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr, |
static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr, |
1176 |
}; |
}; |
1177 |
#endif |
#endif |
1178 |
|
|
|
static void pmac_set_irq(PCIDevice *d, int irq_num, int level) |
|
|
{ |
|
|
openpic_t *openpic; |
|
|
/* XXX: we do not simulate the hardware - we rely on the BIOS to |
|
|
set correctly for irq line field */ |
|
|
openpic = d->bus->openpic; |
|
|
#ifdef TARGET_PPC |
|
|
if (openpic) |
|
|
openpic_set_irq(openpic, d->config[PCI_INTERRUPT_LINE], level); |
|
|
#endif |
|
|
} |
|
|
|
|
|
void pci_pmac_set_openpic(PCIBus *bus, openpic_t *openpic) |
|
|
{ |
|
|
bus->openpic = openpic; |
|
|
} |
|
|
|
|
1179 |
PCIBus *pci_pmac_init(void) |
PCIBus *pci_pmac_init(void) |
1180 |
{ |
{ |
1181 |
PCIBus *s; |
PCIBus *s; |
1185 |
/* Use values found on a real PowerMac */ |
/* Use values found on a real PowerMac */ |
1186 |
/* Uninorth main bus */ |
/* Uninorth main bus */ |
1187 |
s = pci_register_bus(); |
s = pci_register_bus(); |
1188 |
s->set_irq = pmac_set_irq; |
s->set_irq = pci_set_irq_simple; |
1189 |
|
|
1190 |
pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read, |
pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read, |
1191 |
pci_unin_main_config_write, s); |
pci_unin_main_config_write, s); |
1288 |
d->config[0x0E] = 0x00; // header_type |
d->config[0x0E] = 0x00; // header_type |
1289 |
d->config[0x34] = 0x00; // capabilities_pointer |
d->config[0x34] = 0x00; // capabilities_pointer |
1290 |
#endif |
#endif |
|
|
|
|
#if 0 // Grackle ? |
|
|
/* same values as PearPC - check this */ |
|
|
d->config[0x00] = 0x11; // vendor_id |
|
|
d->config[0x01] = 0x10; |
|
|
d->config[0x02] = 0x26; // device_id |
|
|
d->config[0x03] = 0x00; |
|
|
d->config[0x08] = 0x02; // revision |
|
|
d->config[0x0a] = 0x04; // class_sub = pci2pci |
|
|
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
|
|
d->config[0x0e] = 0x01; // header_type |
|
|
|
|
|
d->config[0x18] = 0x0; // primary_bus |
|
|
d->config[0x19] = 0x1; // secondary_bus |
|
|
d->config[0x1a] = 0x1; // subordinate_bus |
|
|
d->config[0x1c] = 0x10; // io_base |
|
|
d->config[0x1d] = 0x20; // io_limit |
|
|
|
|
|
d->config[0x20] = 0x80; // memory_base |
|
|
d->config[0x21] = 0x80; |
|
|
d->config[0x22] = 0x90; // memory_limit |
|
|
d->config[0x23] = 0x80; |
|
|
|
|
|
d->config[0x24] = 0x00; // prefetchable_memory_base |
|
|
d->config[0x25] = 0x84; |
|
|
d->config[0x26] = 0x00; // prefetchable_memory_limit |
|
|
d->config[0x27] = 0x85; |
|
|
#endif |
|
1291 |
return s; |
return s; |
1292 |
} |
} |
1293 |
|
|