159 |
uint32_t pcsr; /* CPU sensitivity register */ |
uint32_t pcsr; /* CPU sensitivity register */ |
160 |
IRQ_queue_t raised; |
IRQ_queue_t raised; |
161 |
IRQ_queue_t servicing; |
IRQ_queue_t servicing; |
162 |
CPUState *env; /* Needed if we did SMP */ |
CPUState *env; |
163 |
} IRQ_dst_t; |
} IRQ_dst_t; |
164 |
|
|
165 |
struct openpic_t { |
struct openpic_t { |
265 |
if (priority > dst->raised.priority) { |
if (priority > dst->raised.priority) { |
266 |
IRQ_get_next(opp, &dst->raised); |
IRQ_get_next(opp, &dst->raised); |
267 |
DPRINTF("Raise CPU IRQ\n"); |
DPRINTF("Raise CPU IRQ\n"); |
268 |
/* XXX: choose the correct cpu */ |
cpu_interrupt(dst->env, CPU_INTERRUPT_HARD); |
|
cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD); |
|
269 |
} |
} |
270 |
} |
} |
271 |
|
|
781 |
src = &opp->src[n_IRQ]; |
src = &opp->src[n_IRQ]; |
782 |
if (IPVP_PRIORITY(src->ipvp) > dst->servicing.priority) { |
if (IPVP_PRIORITY(src->ipvp) > dst->servicing.priority) { |
783 |
DPRINTF("Raise CPU IRQ\n"); |
DPRINTF("Raise CPU IRQ\n"); |
784 |
/* XXX: choose cpu */ |
cpu_interrupt(dst->env, CPU_INTERRUPT_HARD); |
|
cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD); |
|
785 |
} |
} |
786 |
} |
} |
787 |
break; |
break; |
963 |
#endif |
#endif |
964 |
} |
} |
965 |
|
|
966 |
openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus) |
openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, |
967 |
|
CPUPPCState **envp) |
968 |
{ |
{ |
969 |
openpic_t *opp; |
openpic_t *opp; |
970 |
uint8_t *pci_conf; |
uint8_t *pci_conf; |
1018 |
for (; i < MAX_IRQ; i++) { |
for (; i < MAX_IRQ; i++) { |
1019 |
opp->src[i].type = IRQ_INTERNAL; |
opp->src[i].type = IRQ_INTERNAL; |
1020 |
} |
} |
1021 |
|
for (i = 0; i < nb_cpus; i++) |
1022 |
|
opp->dst[i].env = envp[i]; |
1023 |
openpic_reset(opp); |
openpic_reset(opp); |
1024 |
if (pmem_index) |
if (pmem_index) |
1025 |
*pmem_index = opp->mem_index; |
*pmem_index = opp->mem_index; |