47 |
#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ |
#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ |
48 |
#define EN0_RSARHI 0x09 /* Remote start address reg 1 */ |
#define EN0_RSARHI 0x09 /* Remote start address reg 1 */ |
49 |
#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ |
#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ |
50 |
|
#define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */ |
51 |
#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ |
#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ |
52 |
|
#define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */ |
53 |
#define EN0_RSR 0x0c /* rx status reg RD */ |
#define EN0_RSR 0x0c /* rx status reg RD */ |
54 |
#define EN0_RXCR 0x0c /* RX configuration reg WR */ |
#define EN0_RXCR 0x0c /* RX configuration reg WR */ |
55 |
#define EN0_TXCR 0x0d /* TX configuration reg WR */ |
#define EN0_TXCR 0x0d /* TX configuration reg WR */ |
66 |
#define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */ |
#define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */ |
67 |
#define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */ |
#define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */ |
68 |
|
|
69 |
|
#define EN3_CONFIG0 0x33 |
70 |
|
#define EN3_CONFIG1 0x34 |
71 |
|
#define EN3_CONFIG2 0x35 |
72 |
|
#define EN3_CONFIG3 0x36 |
73 |
|
|
74 |
/* Register accessed at EN_CMD, the 8390 base addr. */ |
/* Register accessed at EN_CMD, the 8390 base addr. */ |
75 |
#define E8390_STOP 0x01 /* Stop and reset the chip */ |
#define E8390_STOP 0x01 /* Stop and reset the chip */ |
76 |
#define E8390_START 0x02 /* Start the chip, clear reset */ |
#define E8390_START 0x02 /* Start the chip, clear reset */ |
454 |
case EN2_STOPPG: |
case EN2_STOPPG: |
455 |
ret = s->stop >> 8; |
ret = s->stop >> 8; |
456 |
break; |
break; |
457 |
|
case EN0_RTL8029ID0: |
458 |
|
ret = 0x50; |
459 |
|
break; |
460 |
|
case EN0_RTL8029ID1: |
461 |
|
ret = 0x43; |
462 |
|
break; |
463 |
|
case EN3_CONFIG0: |
464 |
|
ret = 0; /* 10baseT media */ |
465 |
|
break; |
466 |
|
case EN3_CONFIG2: |
467 |
|
ret = 0x40; /* 10baseT active */ |
468 |
|
break; |
469 |
|
case EN3_CONFIG3: |
470 |
|
ret = 0x40; /* Full duplex */ |
471 |
|
break; |
472 |
default: |
default: |
473 |
ret = 0x00; |
ret = 0x00; |
474 |
break; |
break; |