/[qemu]/qemu/hw/mips_r4k.c
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Diff of /qemu/hw/mips_r4k.c

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revision 1.9 by bellard, Sun Aug 21 09:41:56 2005 UTC revision 1.10 by bellard, Mon Nov 21 23:29:55 2005 UTC
# Line 11  static PITState *pit; Line 11  static PITState *pit;
11    
12  static void pic_irq_request(void *opaque, int level)  static void pic_irq_request(void *opaque, int level)
13  {  {
14        CPUState *env = first_cpu;
15      if (level) {      if (level) {
16          cpu_single_env->CP0_Cause |= 0x00000400;          env->CP0_Cause |= 0x00000400;
17          cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);          cpu_interrupt(env, CPU_INTERRUPT_HARD);
18      } else {      } else {
19          cpu_single_env->CP0_Cause &= ~0x00000400;          env->CP0_Cause &= ~0x00000400;
20          cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);          cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
21      }      }
22  }  }
23    
# Line 74  void cpu_mips_store_count (CPUState *env Line 75  void cpu_mips_store_count (CPUState *env
75  void cpu_mips_store_compare (CPUState *env, uint32_t value)  void cpu_mips_store_compare (CPUState *env, uint32_t value)
76  {  {
77      cpu_mips_update_count(env, cpu_mips_get_count(env), value);      cpu_mips_update_count(env, cpu_mips_get_count(env), value);
78      cpu_single_env->CP0_Cause &= ~0x00008000;      env->CP0_Cause &= ~0x00008000;
79      cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);      cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
80  }  }
81    
82  static void mips_timer_cb (void *opaque)  static void mips_timer_cb (void *opaque)
# Line 89  static void mips_timer_cb (void *opaque) Line 90  static void mips_timer_cb (void *opaque)
90      }      }
91  #endif  #endif
92      cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);      cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
93      cpu_single_env->CP0_Cause |= 0x00008000;      env->CP0_Cause |= 0x00008000;
94      cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);      cpu_interrupt(env, CPU_INTERRUPT_HARD);
95  }  }
96    
97  void cpu_mips_clock_init (CPUState *env)  void cpu_mips_clock_init (CPUState *env)
# Line 181  void mips_r4k_init (int ram_size, int vg Line 182  void mips_r4k_init (int ram_size, int vg
182      int io_memory;      int io_memory;
183      int linux_boot;      int linux_boot;
184      int ret;      int ret;
185        CPUState *env;
186    
187      printf("%s: start\n", __func__);      printf("%s: start\n", __func__);
188      linux_boot = (kernel_filename != NULL);      linux_boot = (kernel_filename != NULL);
189    
190        env = cpu_init();
191        register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
192    
193      /* allocate RAM */      /* allocate RAM */
194      cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);      cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
195      bios_offset = ram_size + vga_ram_size;      bios_offset = ram_size + vga_ram_size;
# Line 198  void mips_r4k_init (int ram_size, int vg Line 204  void mips_r4k_init (int ram_size, int vg
204                                   BIOS_SIZE, bios_offset | IO_MEM_ROM);                                   BIOS_SIZE, bios_offset | IO_MEM_ROM);
205  #if 0  #if 0
206      memcpy(phys_ram_base + 0x10000, phys_ram_base + bios_offset, BIOS_SIZE);      memcpy(phys_ram_base + 0x10000, phys_ram_base + bios_offset, BIOS_SIZE);
207      cpu_single_env->PC = 0x80010004;      env->PC = 0x80010004;
208  #else  #else
209      cpu_single_env->PC = 0xBFC00004;      env->PC = 0xBFC00004;
210  #endif  #endif
211      if (linux_boot) {      if (linux_boot) {
212          kernel_base = KERNEL_LOAD_ADDR;          kernel_base = KERNEL_LOAD_ADDR;
# Line 226  void mips_r4k_init (int ram_size, int vg Line 232  void mips_r4k_init (int ram_size, int vg
232              initrd_base = 0;              initrd_base = 0;
233              initrd_size = 0;              initrd_size = 0;
234          }          }
235          cpu_single_env->PC = KERNEL_LOAD_ADDR;          env->PC = KERNEL_LOAD_ADDR;
236      } else {      } else {
237          kernel_base = 0;          kernel_base = 0;
238          kernel_size = 0;          kernel_size = 0;
# Line 235  void mips_r4k_init (int ram_size, int vg Line 241  void mips_r4k_init (int ram_size, int vg
241      }      }
242    
243      /* Init internal devices */      /* Init internal devices */
244      cpu_mips_clock_init(cpu_single_env);      cpu_mips_clock_init(env);
245      cpu_mips_irqctrl_init();      cpu_mips_irqctrl_init();
246    
247      /* Register 64 KB of ISA IO space at 0x14000000 */      /* Register 64 KB of ISA IO space at 0x14000000 */
# Line 243  void mips_r4k_init (int ram_size, int vg Line 249  void mips_r4k_init (int ram_size, int vg
249      cpu_register_physical_memory(0x14000000, 0x00010000, io_memory);      cpu_register_physical_memory(0x14000000, 0x00010000, io_memory);
250      isa_mem_base = 0x10000000;      isa_mem_base = 0x10000000;
251    
252      isa_pic = pic_init(pic_irq_request, cpu_single_env);      isa_pic = pic_init(pic_irq_request, env);
253      pit = pit_init(0x40, 0);      pit = pit_init(0x40, 0);
254      serial_init(0x3f8, 4, serial_hds[0]);      serial_init(0x3f8, 4, serial_hds[0]);
255      vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size,      vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size,

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  Added in v.1.10

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