33 |
#define DPRINTF(fmt, args...) |
#define DPRINTF(fmt, args...) |
34 |
#endif |
#endif |
35 |
|
|
36 |
#define IOMMU_NREGS (3*4096) |
#define IOMMU_NREGS (3*4096/4) |
37 |
|
#define IOMMU_CTRL (0x0000 >> 2) |
38 |
#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ |
#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ |
39 |
#define IOMMU_CTRL_VERS 0x0f000000 /* Version */ |
#define IOMMU_CTRL_VERS 0x0f000000 /* Version */ |
40 |
|
#define IOMMU_VERSION 0x04000000 |
41 |
#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */ |
#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */ |
42 |
#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */ |
#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */ |
43 |
#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */ |
#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */ |
48 |
#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */ |
#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */ |
49 |
#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */ |
#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */ |
50 |
#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */ |
#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */ |
51 |
|
#define IOMMU_CTRL_MASK 0x0000001d |
52 |
|
|
53 |
|
#define IOMMU_BASE (0x0004 >> 2) |
54 |
|
#define IOMMU_BASE_MASK 0x07fffc00 |
55 |
|
|
56 |
|
#define IOMMU_TLBFLUSH (0x0014 >> 2) |
57 |
|
#define IOMMU_TLBFLUSH_MASK 0xffffffff |
58 |
|
|
59 |
|
#define IOMMU_PGFLUSH (0x0018 >> 2) |
60 |
|
#define IOMMU_PGFLUSH_MASK 0xffffffff |
61 |
|
|
62 |
|
#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */ |
63 |
|
#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ |
64 |
|
#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ |
65 |
|
#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */ |
66 |
|
#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */ |
67 |
|
#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ |
68 |
|
#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ |
69 |
|
#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses |
70 |
|
produced by this device as pure |
71 |
|
physical. */ |
72 |
|
#define IOMMU_SBCFG_MASK 0x00010003 |
73 |
|
|
74 |
|
#define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */ |
75 |
|
#define IOMMU_ARBEN_MASK 0x001f0000 |
76 |
|
#define IOMMU_MID 0x00000008 |
77 |
|
|
78 |
/* The format of an iopte in the page tables */ |
/* The format of an iopte in the page tables */ |
79 |
#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */ |
#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */ |
115 |
saddr = (addr - s->addr) >> 2; |
saddr = (addr - s->addr) >> 2; |
116 |
DPRINTF("write reg[%d] = %x\n", saddr, val); |
DPRINTF("write reg[%d] = %x\n", saddr, val); |
117 |
switch (saddr) { |
switch (saddr) { |
118 |
case 0: |
case IOMMU_CTRL: |
119 |
switch (val & IOMMU_CTRL_RNGE) { |
switch (val & IOMMU_CTRL_RNGE) { |
120 |
case IOMMU_RNGE_16MB: |
case IOMMU_RNGE_16MB: |
121 |
s->iostart = 0xff000000; |
s->iostart = 0xff000000; |
144 |
break; |
break; |
145 |
} |
} |
146 |
DPRINTF("iostart = %x\n", s->iostart); |
DPRINTF("iostart = %x\n", s->iostart); |
147 |
/* Fall through */ |
s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION); |
148 |
|
break; |
149 |
|
case IOMMU_BASE: |
150 |
|
s->regs[saddr] = val & IOMMU_BASE_MASK; |
151 |
|
break; |
152 |
|
case IOMMU_TLBFLUSH: |
153 |
|
DPRINTF("tlb flush %x\n", val); |
154 |
|
s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; |
155 |
|
break; |
156 |
|
case IOMMU_PGFLUSH: |
157 |
|
DPRINTF("page flush %x\n", val); |
158 |
|
s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; |
159 |
|
break; |
160 |
|
case IOMMU_SBCFG0: |
161 |
|
case IOMMU_SBCFG1: |
162 |
|
case IOMMU_SBCFG2: |
163 |
|
case IOMMU_SBCFG3: |
164 |
|
s->regs[saddr] = val & IOMMU_SBCFG_MASK; |
165 |
|
break; |
166 |
|
case IOMMU_ARBEN: |
167 |
|
// XXX implement SBus probing: fault when reading unmapped |
168 |
|
// addresses, fault cause and address stored to MMU/IOMMU |
169 |
|
s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; |
170 |
|
break; |
171 |
default: |
default: |
172 |
s->regs[saddr] = val; |
s->regs[saddr] = val; |
173 |
break; |
break; |
235 |
|
|
236 |
memset(s->regs, 0, IOMMU_NREGS * 4); |
memset(s->regs, 0, IOMMU_NREGS * 4); |
237 |
s->iostart = 0; |
s->iostart = 0; |
238 |
|
s->regs[0] = IOMMU_VERSION; |
239 |
} |
} |
240 |
|
|
241 |
void *iommu_init(uint32_t addr) |
void *iommu_init(uint32_t addr) |