/[qemu]/qemu/hw/i8259.c
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revision 1.15 by bellard, Sun Jun 5 14:50:22 2005 UTC revision 1.16 by bellard, Sat Jul 2 18:11:44 2005 UTC
# Line 46  typedef struct PicState { Line 46  typedef struct PicState {
46      uint8_t init4; /* true if 4 byte init */      uint8_t init4; /* true if 4 byte init */
47      uint8_t elcr; /* PIIX edge/trigger selection*/      uint8_t elcr; /* PIIX edge/trigger selection*/
48      uint8_t elcr_mask;      uint8_t elcr_mask;
49        PicState2 *pics_state;
50  } PicState;  } PicState;
51    
52  /* 0 is master pic, 1 is slave pic */  struct PicState2 {
53  static PicState pics[2];      /* 0 is master pic, 1 is slave pic */
54        /* XXX: better separation between the two pics */
55        PicState pics[2];
56        IRQRequestFunc *irq_request;
57        void *irq_request_opaque;
58    };
59    
60  #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)  #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
61  static int irq_level[16];  static int irq_level[16];
# Line 110  static int pic_get_irq(PicState *s) Line 116  static int pic_get_irq(PicState *s)
116         master, the IRQ coming from the slave is not taken into account         master, the IRQ coming from the slave is not taken into account
117         for the priority computation. */         for the priority computation. */
118      mask = s->isr;      mask = s->isr;
119      if (s->special_fully_nested_mode && s == &pics[0])      if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
120          mask &= ~(1 << 2);          mask &= ~(1 << 2);
121      cur_priority = get_priority(s, mask);      cur_priority = get_priority(s, mask);
122      if (priority < cur_priority) {      if (priority < cur_priority) {
# Line 123  static int pic_get_irq(PicState *s) Line 129  static int pic_get_irq(PicState *s)
129    
130  /* raise irq to CPU if necessary. must be called every time the active  /* raise irq to CPU if necessary. must be called every time the active
131     irq may change */     irq may change */
132  static void pic_update_irq(void)  /* XXX: should not export it, but it is needed for an APIC kludge */
133    void pic_update_irq(PicState2 *s)
134  {  {
135      int irq2, irq;      int irq2, irq;
136    
137      /* first look at slave pic */      /* first look at slave pic */
138      irq2 = pic_get_irq(&pics[1]);      irq2 = pic_get_irq(&s->pics[1]);
139      if (irq2 >= 0) {      if (irq2 >= 0) {
140          /* if irq request by slave pic, signal master PIC */          /* if irq request by slave pic, signal master PIC */
141          pic_set_irq1(&pics[0], 2, 1);          pic_set_irq1(&s->pics[0], 2, 1);
142          pic_set_irq1(&pics[0], 2, 0);          pic_set_irq1(&s->pics[0], 2, 0);
143      }      }
144      /* look at requested irq */      /* look at requested irq */
145      irq = pic_get_irq(&pics[0]);      irq = pic_get_irq(&s->pics[0]);
146      if (irq >= 0) {      if (irq >= 0) {
147  #if defined(DEBUG_PIC)  #if defined(DEBUG_PIC)
148          {          {
149              int i;              int i;
150              for(i = 0; i < 2; i++) {              for(i = 0; i < 2; i++) {
151                  printf("pic%d: imr=%x irr=%x padd=%d\n",                  printf("pic%d: imr=%x irr=%x padd=%d\n",
152                         i, pics[i].imr, pics[i].irr, pics[i].priority_add);                         i, s->pics[i].imr, s->pics[i].irr,
153                           s->pics[i].priority_add);
154                                    
155              }              }
156          }          }
157          printf("pic: cpu_interrupt\n");          printf("pic: cpu_interrupt\n");
158  #endif  #endif
159          cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);          s->irq_request(s->irq_request_opaque, 1);
160      }      }
161  }  }
162    
# Line 156  static void pic_update_irq(void) Line 164  static void pic_update_irq(void)
164  int64_t irq_time[16];  int64_t irq_time[16];
165  #endif  #endif
166    
167  void pic_set_irq(int irq, int level)  void pic_set_irq_new(void *opaque, int irq, int level)
168  {  {
169        PicState2 *s = opaque;
170    
171  #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)  #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
172      if (level != irq_level[irq]) {      if (level != irq_level[irq]) {
173  #if defined(DEBUG_PIC)  #if defined(DEBUG_PIC)
# Line 175  void pic_set_irq(int irq, int level) Line 185  void pic_set_irq(int irq, int level)
185          irq_time[irq] = qemu_get_clock(vm_clock);          irq_time[irq] = qemu_get_clock(vm_clock);
186      }      }
187  #endif  #endif
188      pic_set_irq1(&pics[irq >> 3], irq & 7, level);      pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
189      pic_update_irq();      pic_update_irq(s);
190  }  }
191    
192  /* this function should be used to have the controller context */  /* obsolete function */
193  void pic_set_irq_new(void *opaque, int irq, int level)  void pic_set_irq(int irq, int level)
194  {  {
195      pic_set_irq(irq, level);      pic_set_irq_new(isa_pic, irq, level);
196  }  }
197    
198  /* acknowledge interrupt 'irq' */  /* acknowledge interrupt 'irq' */
# Line 199  static inline void pic_intack(PicState * Line 209  static inline void pic_intack(PicState *
209          s->irr &= ~(1 << irq);          s->irr &= ~(1 << irq);
210  }  }
211    
212  int cpu_get_pic_interrupt(CPUState *env)  int pic_read_irq(PicState2 *s)
213  {  {
214      int irq, irq2, intno;      int irq, irq2, intno;
215    
216  #ifdef TARGET_X86_64      irq = pic_get_irq(&s->pics[0]);
     intno = apic_get_interrupt(env);  
     if (intno >= 0) {  
         /* set irq request if a PIC irq is still pending */  
         /* XXX: improve that */  
         pic_update_irq();  
         return intno;  
     }  
 #endif  
     /* read the irq from the PIC */  
   
     irq = pic_get_irq(&pics[0]);  
217      if (irq >= 0) {      if (irq >= 0) {
218          pic_intack(&pics[0], irq);          pic_intack(&s->pics[0], irq);
219          if (irq == 2) {          if (irq == 2) {
220              irq2 = pic_get_irq(&pics[1]);              irq2 = pic_get_irq(&s->pics[1]);
221              if (irq2 >= 0) {              if (irq2 >= 0) {
222                  pic_intack(&pics[1], irq2);                  pic_intack(&s->pics[1], irq2);
223              } else {              } else {
224                  /* spurious IRQ on slave controller */                  /* spurious IRQ on slave controller */
225                  irq2 = 7;                  irq2 = 7;
226              }              }
227              intno = pics[1].irq_base + irq2;              intno = s->pics[1].irq_base + irq2;
228              irq = irq2 + 8;              irq = irq2 + 8;
229          } else {          } else {
230              intno = pics[0].irq_base + irq;              intno = s->pics[0].irq_base + irq;
231          }          }
232      } else {      } else {
233          /* spurious IRQ on host controller */          /* spurious IRQ on host controller */
234          irq = 7;          irq = 7;
235          intno = pics[0].irq_base + irq;          intno = s->pics[0].irq_base + irq;
236      }      }
237      pic_update_irq();      pic_update_irq(s);
238                    
239  #ifdef DEBUG_IRQ_LATENCY  #ifdef DEBUG_IRQ_LATENCY
240      printf("IRQ%d latency=%0.3fus\n",      printf("IRQ%d latency=%0.3fus\n",
# Line 251  int cpu_get_pic_interrupt(CPUState *env) Line 250  int cpu_get_pic_interrupt(CPUState *env)
250  static void pic_reset(void *opaque)  static void pic_reset(void *opaque)
251  {  {
252      PicState *s = opaque;      PicState *s = opaque;
     int tmp;  
253    
254      tmp = s->elcr_mask;      s->last_irr = 0;
255      memset(s, 0, sizeof(PicState));      s->irr = 0;
256      s->elcr_mask = tmp;      s->imr = 0;
257        s->isr = 0;
258        s->priority_add = 0;
259        s->irq_base = 0;
260        s->read_reg_select = 0;
261        s->poll = 0;
262        s->special_mask = 0;
263        s->init_state = 0;
264        s->auto_eoi = 0;
265        s->rotate_on_auto_eoi = 0;
266        s->special_fully_nested_mode = 0;
267        s->init4 = 0;
268        s->elcr = 0;
269  }  }
270    
271  static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)  static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
# Line 272  static void pic_ioport_write(void *opaqu Line 282  static void pic_ioport_write(void *opaqu
282              /* init */              /* init */
283              pic_reset(s);              pic_reset(s);
284              /* deassert a pending interrupt */              /* deassert a pending interrupt */
285              cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);              s->pics_state->irq_request(s->pics_state->irq_request_opaque, 0);
   
286              s->init_state = 1;              s->init_state = 1;
287              s->init4 = val & 1;              s->init4 = val & 1;
288              if (val & 0x02)              if (val & 0x02)
# Line 302  static void pic_ioport_write(void *opaqu Line 311  static void pic_ioport_write(void *opaqu
311                      s->isr &= ~(1 << irq);                      s->isr &= ~(1 << irq);
312                      if (cmd == 5)                      if (cmd == 5)
313                          s->priority_add = (irq + 1) & 7;                          s->priority_add = (irq + 1) & 7;
314                      pic_update_irq();                      pic_update_irq(s->pics_state);
315                  }                  }
316                  break;                  break;
317              case 3:              case 3:
318                  irq = val & 7;                  irq = val & 7;
319                  s->isr &= ~(1 << irq);                  s->isr &= ~(1 << irq);
320                  pic_update_irq();                  pic_update_irq(s->pics_state);
321                  break;                  break;
322              case 6:              case 6:
323                  s->priority_add = (val + 1) & 7;                  s->priority_add = (val + 1) & 7;
324                  pic_update_irq();                  pic_update_irq(s->pics_state);
325                  break;                  break;
326              case 7:              case 7:
327                  irq = val & 7;                  irq = val & 7;
328                  s->isr &= ~(1 << irq);                  s->isr &= ~(1 << irq);
329                  s->priority_add = (irq + 1) & 7;                  s->priority_add = (irq + 1) & 7;
330                  pic_update_irq();                  pic_update_irq(s->pics_state);
331                  break;                  break;
332              default:              default:
333                  /* no operation */                  /* no operation */
# Line 330  static void pic_ioport_write(void *opaqu Line 339  static void pic_ioport_write(void *opaqu
339          case 0:          case 0:
340              /* normal mode */              /* normal mode */
341              s->imr = val;              s->imr = val;
342              pic_update_irq();              pic_update_irq(s->pics_state);
343              break;              break;
344          case 1:          case 1:
345              s->irq_base = val & 0xf8;              s->irq_base = val & 0xf8;
# Line 359  static uint32_t pic_poll_read (PicState Line 368  static uint32_t pic_poll_read (PicState
368      ret = pic_get_irq(s);      ret = pic_get_irq(s);
369      if (ret >= 0) {      if (ret >= 0) {
370          if (addr1 >> 7) {          if (addr1 >> 7) {
371              pics[0].isr &= ~(1 << 2);              s->pics_state->pics[0].isr &= ~(1 << 2);
372              pics[0].irr &= ~(1 << 2);              s->pics_state->pics[0].irr &= ~(1 << 2);
373          }          }
374          s->irr &= ~(1 << ret);          s->irr &= ~(1 << ret);
375          s->isr &= ~(1 << ret);          s->isr &= ~(1 << ret);
376          if (addr1 >> 7 || ret != 2)          if (addr1 >> 7 || ret != 2)
377              pic_update_irq();              pic_update_irq(s->pics_state);
378      } else {      } else {
379          ret = 0x07;          ret = 0x07;
380          pic_update_irq();          pic_update_irq(s->pics_state);
381      }      }
382    
383      return ret;      return ret;
# Line 402  static uint32_t pic_ioport_read(void *op Line 411  static uint32_t pic_ioport_read(void *op
411  }  }
412    
413  /* memory mapped interrupt status */  /* memory mapped interrupt status */
414  uint32_t pic_intack_read(CPUState *env)  /* XXX: may be the same than pic_read_irq() */
415    uint32_t pic_intack_read(PicState2 *s)
416  {  {
417      int ret;      int ret;
418    
419      ret = pic_poll_read(&pics[0], 0x00);      ret = pic_poll_read(&s->pics[0], 0x00);
420      if (ret == 2)      if (ret == 2)
421          ret = pic_poll_read(&pics[1], 0x80) + 8;          ret = pic_poll_read(&s->pics[1], 0x80) + 8;
422      /* Prepare for ISR read */      /* Prepare for ISR read */
423      pics[0].read_reg_select = 1;      s->pics[0].read_reg_select = 1;
424            
425      return ret;      return ret;
426  }  }
# Line 490  void pic_info(void) Line 500  void pic_info(void)
500  {  {
501      int i;      int i;
502      PicState *s;      PicState *s;
503        
504        if (!isa_pic)
505            return;
506    
507      for(i=0;i<2;i++) {      for(i=0;i<2;i++) {
508          s = &pics[i];          s = &isa_pic->pics[i];
509          term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",          term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
510                      i, s->irr, s->imr, s->isr, s->priority_add,                      i, s->irr, s->imr, s->isr, s->priority_add,
511                      s->irq_base, s->read_reg_select, s->elcr,                      s->irq_base, s->read_reg_select, s->elcr,
# Line 517  void irq_info(void) Line 530  void irq_info(void)
530  #endif  #endif
531  }  }
532    
533  void pic_init(void)  PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque)
534  {  {
535      pic_init1(0x20, 0x4d0, &pics[0]);      PicState2 *s;
536      pic_init1(0xa0, 0x4d1, &pics[1]);      s = qemu_mallocz(sizeof(PicState2));
537      pics[0].elcr_mask = 0xf8;      if (!s)
538      pics[1].elcr_mask = 0xde;          return NULL;
539        pic_init1(0x20, 0x4d0, &s->pics[0]);
540        pic_init1(0xa0, 0x4d1, &s->pics[1]);
541        s->pics[0].elcr_mask = 0xf8;
542        s->pics[1].elcr_mask = 0xde;
543        s->irq_request = irq_request;
544        s->irq_request_opaque = irq_request_opaque;
545        s->pics[0].pics_state = s;
546        s->pics[1].pics_state = s;
547        return s;
548  }  }
   

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