95 |
} fdrive_t; |
} fdrive_t; |
96 |
|
|
97 |
#ifdef TARGET_SPARC |
#ifdef TARGET_SPARC |
98 |
|
/* XXX: suppress those hacks */ |
99 |
#define DMA_read_memory(a,b,c,d) |
#define DMA_read_memory(a,b,c,d) |
100 |
#define DMA_write_memory(a,b,c,d) |
#define DMA_write_memory(a,b,c,d) |
101 |
#define DMA_register_channel(a,b,c) |
void DMA_register_channel (int nchan, |
102 |
|
DMA_transfer_handler transfer_handler, |
103 |
|
void *opaque) |
104 |
|
{ |
105 |
|
} |
106 |
#define DMA_hold_DREQ(a) |
#define DMA_hold_DREQ(a) |
107 |
#define DMA_release_DREQ(a) |
#define DMA_release_DREQ(a) |
108 |
#define DMA_get_channel_mode(a) (0) |
#define DMA_get_channel_mode(a) (0) |
474 |
} |
} |
475 |
} |
} |
476 |
|
|
477 |
|
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg) |
478 |
|
{ |
479 |
|
return fdctrl_read(opaque, reg); |
480 |
|
} |
481 |
|
|
482 |
|
static void fdctrl_write_mem (void *opaque, |
483 |
|
target_phys_addr_t reg, uint32_t value) |
484 |
|
{ |
485 |
|
fdctrl_write(opaque, reg, value); |
486 |
|
} |
487 |
|
|
488 |
static CPUReadMemoryFunc *fdctrl_mem_read[3] = { |
static CPUReadMemoryFunc *fdctrl_mem_read[3] = { |
489 |
fdctrl_read, |
fdctrl_read_mem, |
490 |
fdctrl_read, |
fdctrl_read_mem, |
491 |
fdctrl_read, |
fdctrl_read_mem, |
492 |
}; |
}; |
493 |
|
|
494 |
static CPUWriteMemoryFunc *fdctrl_mem_write[3] = { |
static CPUWriteMemoryFunc *fdctrl_mem_write[3] = { |
495 |
fdctrl_write, |
fdctrl_write_mem, |
496 |
fdctrl_write, |
fdctrl_write_mem, |
497 |
fdctrl_write, |
fdctrl_write_mem, |
498 |
}; |
}; |
499 |
|
|
500 |
static void fd_change_cb (void *opaque) |
static void fd_change_cb (void *opaque) |