800 |
s->cirrus_blt_srcpitch, |
s->cirrus_blt_srcpitch, |
801 |
s->cirrus_blt_dstaddr, |
s->cirrus_blt_dstaddr, |
802 |
s->cirrus_blt_srcaddr, |
s->cirrus_blt_srcaddr, |
803 |
s->sr[0x2f]); |
s->gr[0x2f]); |
804 |
#endif |
#endif |
805 |
|
|
806 |
switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) { |
switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) { |
1042 |
else |
else |
1043 |
offset <<= 12; |
offset <<= 12; |
1044 |
|
|
1045 |
if (s->vram_size <= offset) |
if (s->real_vram_size <= offset) |
1046 |
limit = 0; |
limit = 0; |
1047 |
else |
else |
1048 |
limit = s->vram_size - offset; |
limit = s->real_vram_size - offset; |
1049 |
|
|
1050 |
if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) { |
if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) { |
1051 |
if (limit > 0x8000) { |
if (limit > 0x8000) { |
1213 |
#endif |
#endif |
1214 |
break; |
break; |
1215 |
case 0x17: // Configuration Readback and Extended Control |
case 0x17: // Configuration Readback and Extended Control |
1216 |
s->sr[reg_index] = reg_value; |
s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7); |
1217 |
cirrus_update_memory_access(s); |
cirrus_update_memory_access(s); |
1218 |
break; |
break; |
1219 |
default: |
default: |