96 |
static int apic_io_memory; |
static int apic_io_memory; |
97 |
static APICState *first_local_apic = NULL; |
static APICState *first_local_apic = NULL; |
98 |
static int last_apic_id = 0; |
static int last_apic_id = 0; |
|
static IOAPICState *ioapic_state; |
|
99 |
|
|
100 |
static void apic_init_ipi(APICState *s); |
static void apic_init_ipi(APICState *s); |
101 |
static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); |
static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); |
126 |
return; |
return; |
127 |
|
|
128 |
case APIC_DM_EXTINT: |
case APIC_DM_EXTINT: |
129 |
/* XXX: implement */ |
/* handled in I/O APIC code */ |
130 |
break; |
break; |
131 |
|
|
132 |
default: |
default: |
753 |
|
|
754 |
static void ioapic_service(IOAPICState *s) |
static void ioapic_service(IOAPICState *s) |
755 |
{ |
{ |
756 |
|
uint8_t i; |
757 |
|
uint8_t trig_mode; |
758 |
uint8_t vector; |
uint8_t vector; |
759 |
|
uint8_t delivery_mode; |
760 |
uint32_t mask; |
uint32_t mask; |
761 |
uint64_t entry; |
uint64_t entry; |
762 |
uint8_t dest; |
uint8_t dest; |
763 |
uint8_t dest_mode; |
uint8_t dest_mode; |
764 |
|
uint8_t polarity; |
765 |
|
|
766 |
for (vector = 0; vector < IOAPIC_NUM_PINS; vector++) { |
for (i = 0; i < IOAPIC_NUM_PINS; i++) { |
767 |
mask = 1 << vector; |
mask = 1 << i; |
768 |
if (s->irr & mask) { |
if (s->irr & mask) { |
769 |
entry = s->ioredtbl[vector]; |
entry = s->ioredtbl[i]; |
770 |
if (!(entry & APIC_LVT_MASKED)) { |
if (!(entry & APIC_LVT_MASKED)) { |
771 |
if (!((entry >> 15) & 1)) |
trig_mode = ((entry >> 15) & 1); |
|
s->irr &= ~mask; |
|
772 |
dest = entry >> 56; |
dest = entry >> 56; |
773 |
dest_mode = (entry >> 11) & 1; |
dest_mode = (entry >> 11) & 1; |
774 |
|
delivery_mode = (entry >> 8) & 7; |
775 |
|
polarity = (entry >> 13) & 1; |
776 |
|
if (trig_mode == APIC_TRIGGER_EDGE) |
777 |
|
s->irr &= ~mask; |
778 |
|
if (delivery_mode == APIC_DM_EXTINT) |
779 |
|
vector = pic_read_irq(isa_pic); |
780 |
|
else |
781 |
|
vector = entry & 0xff; |
782 |
apic_bus_deliver(apic_get_delivery_bitmask(dest, dest_mode), |
apic_bus_deliver(apic_get_delivery_bitmask(dest, dest_mode), |
783 |
(entry >> 8) & 7, entry & 0xff, |
delivery_mode, vector, polarity, trig_mode); |
|
(entry >> 13) & 1, (entry >> 15) & 1); |
|
784 |
} |
} |
785 |
} |
} |
786 |
} |
} |
939 |
IOAPICState *s; |
IOAPICState *s; |
940 |
int io_memory; |
int io_memory; |
941 |
|
|
942 |
s = malloc(sizeof(IOAPICState)); |
s = qemu_mallocz(sizeof(IOAPICState)); |
943 |
if (!s) |
if (!s) |
944 |
return NULL; |
return NULL; |
|
ioapic_state = s; |
|
945 |
ioapic_reset(s); |
ioapic_reset(s); |
946 |
s->id = last_apic_id++; |
s->id = last_apic_id++; |
947 |
|
|