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#ifdef __ia64__ |
#ifdef __ia64__ |
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
{ |
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while (start < stop) { |
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asm volatile ("fc %0" :: "r"(start)); |
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start += 32; |
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} |
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asm volatile (";;sync.i;;srlz.i;;"); |
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} |
} |
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#endif |
#endif |
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} |
} |
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#endif /* __arm__ */ |
#endif /* __arm__ */ |
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#ifdef __ia64 |
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/* Patch instruction with "val" where "mask" has 1 bits. */ |
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static inline void ia64_patch (uint64_t insn_addr, uint64_t mask, uint64_t val) |
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{ |
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uint64_t m0, m1, v0, v1, b0, b1, *b = (uint64_t *) (insn_addr & -16); |
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# define insn_mask ((1UL << 41) - 1) |
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unsigned long shift; |
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b0 = b[0]; b1 = b[1]; |
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shift = 5 + 41 * (insn_addr % 16); /* 5 template, 3 x 41-bit insns */ |
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if (shift >= 64) { |
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m1 = mask << (shift - 64); |
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v1 = val << (shift - 64); |
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} else { |
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m0 = mask << shift; m1 = mask >> (64 - shift); |
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v0 = val << shift; v1 = val >> (64 - shift); |
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b[0] = (b0 & ~m0) | (v0 & m0); |
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} |
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b[1] = (b1 & ~m1) | (v1 & m1); |
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} |
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static inline void ia64_patch_imm60 (uint64_t insn_addr, uint64_t val) |
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{ |
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ia64_patch(insn_addr, |
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0x011ffffe000UL, |
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( ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */ |
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| ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */)); |
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ia64_patch(insn_addr - 1, 0x1fffffffffcUL, val >> 18); |
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} |
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static inline void ia64_imm64 (void *insn, uint64_t val) |
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{ |
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/* Ignore the slot number of the relocation; GCC and Intel |
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toolchains differed for some time on whether IMM64 relocs are |
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against slot 1 (Intel) or slot 2 (GCC). */ |
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uint64_t insn_addr = (uint64_t) insn & ~3UL; |
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ia64_patch(insn_addr + 2, |
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0x01fffefe000UL, |
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( ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */ |
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| ((val & 0x0000000000200000UL) << 0) /* bit 21 -> 21 */ |
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| ((val & 0x00000000001f0000UL) << 6) /* bit 16 -> 22 */ |
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| ((val & 0x000000000000ff80UL) << 20) /* bit 7 -> 27 */ |
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| ((val & 0x000000000000007fUL) << 13) /* bit 0 -> 13 */) |
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); |
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ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22); |
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} |
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static inline void ia64_imm60b (void *insn, uint64_t val) |
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{ |
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/* Ignore the slot number of the relocation; GCC and Intel |
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toolchains differed for some time on whether IMM64 relocs are |
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against slot 1 (Intel) or slot 2 (GCC). */ |
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uint64_t insn_addr = (uint64_t) insn & ~3UL; |
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if (val + ((uint64_t) 1 << 59) >= (1UL << 60)) |
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fprintf(stderr, "%s: value %ld out of IMM60 range\n", |
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__FUNCTION__, (int64_t) val); |
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ia64_patch_imm60(insn_addr + 2, val); |
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} |
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static inline void ia64_imm22 (void *insn, uint64_t val) |
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{ |
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if (val + (1 << 21) >= (1 << 22)) |
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fprintf(stderr, "%s: value %li out of IMM22 range\n", |
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__FUNCTION__, (int64_t)val); |
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ia64_patch((uint64_t) insn, 0x01fffcfe000UL, |
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( ((val & 0x200000UL) << 15) /* bit 21 -> 36 */ |
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| ((val & 0x1f0000UL) << 6) /* bit 16 -> 22 */ |
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| ((val & 0x00ff80UL) << 20) /* bit 7 -> 27 */ |
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| ((val & 0x00007fUL) << 13) /* bit 0 -> 13 */)); |
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} |
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/* Like ia64_imm22(), but also clear bits 20-21. For addl, this has |
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the effect of turning "addl rX=imm22,rY" into "addl |
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rX=imm22,r0". */ |
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static inline void ia64_imm22_r0 (void *insn, uint64_t val) |
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{ |
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if (val + (1 << 21) >= (1 << 22)) |
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fprintf(stderr, "%s: value %li out of IMM22 range\n", |
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__FUNCTION__, (int64_t)val); |
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ia64_patch((uint64_t) insn, 0x01fffcfe000UL | (0x3UL << 20), |
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( ((val & 0x200000UL) << 15) /* bit 21 -> 36 */ |
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| ((val & 0x1f0000UL) << 6) /* bit 16 -> 22 */ |
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| ((val & 0x00ff80UL) << 20) /* bit 7 -> 27 */ |
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| ((val & 0x00007fUL) << 13) /* bit 0 -> 13 */)); |
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} |
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static inline void ia64_imm21b (void *insn, uint64_t val) |
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{ |
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if (val + (1 << 20) >= (1 << 21)) |
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fprintf(stderr, "%s: value %li out of IMM21b range\n", |
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__FUNCTION__, (int64_t)val); |
308 |
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ia64_patch((uint64_t) insn, 0x11ffffe000UL, |
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( ((val & 0x100000UL) << 16) /* bit 20 -> 36 */ |
310 |
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| ((val & 0x0fffffUL) << 13) /* bit 0 -> 13 */)); |
311 |
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} |
312 |
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313 |
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static inline void ia64_nop_b (void *insn) |
314 |
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{ |
315 |
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ia64_patch((uint64_t) insn, (1UL << 41) - 1, 2UL << 37); |
316 |
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} |
317 |
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static inline void ia64_ldxmov(void *insn, uint64_t val) |
319 |
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{ |
320 |
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if (val + (1 << 21) < (1 << 22)) |
321 |
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ia64_patch((uint64_t) insn, 0x1fff80fe000UL, 8UL << 37); |
322 |
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} |
323 |
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static inline int ia64_patch_ltoff(void *insn, uint64_t val, |
325 |
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int relaxable) |
326 |
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{ |
327 |
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if (relaxable && (val + (1 << 21) < (1 << 22))) { |
328 |
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ia64_imm22_r0(insn, val); |
329 |
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return 0; |
330 |
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} |
331 |
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return 1; |
332 |
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} |
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struct ia64_fixup { |
335 |
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struct ia64_fixup *next; |
336 |
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void *addr; /* address that needs to be patched */ |
337 |
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long value; |
338 |
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}; |
339 |
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340 |
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#define IA64_PLT(insn, plt_index) \ |
341 |
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do { \ |
342 |
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struct ia64_fixup *fixup = alloca(sizeof(*fixup)); \ |
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fixup->next = plt_fixes; \ |
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plt_fixes = fixup; \ |
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fixup->addr = (insn); \ |
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fixup->value = (plt_index); \ |
347 |
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plt_offset[(plt_index)] = 1; \ |
348 |
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} while (0) |
349 |
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350 |
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#define IA64_LTOFF(insn, val, relaxable) \ |
351 |
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do { \ |
352 |
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if (ia64_patch_ltoff(insn, val, relaxable)) { \ |
353 |
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struct ia64_fixup *fixup = alloca(sizeof(*fixup)); \ |
354 |
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fixup->next = ltoff_fixes; \ |
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ltoff_fixes = fixup; \ |
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fixup->addr = (insn); \ |
357 |
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fixup->value = (val); \ |
358 |
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} \ |
359 |
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} while (0) |
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361 |
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static inline void ia64_apply_fixes (uint8_t **gen_code_pp, |
362 |
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struct ia64_fixup *ltoff_fixes, |
363 |
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uint64_t gp, |
364 |
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struct ia64_fixup *plt_fixes, |
365 |
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int num_plts, |
366 |
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unsigned long *plt_target, |
367 |
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unsigned int *plt_offset) |
368 |
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{ |
369 |
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static const uint8_t plt_bundle[] = { |
370 |
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0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; movl r1=GP */ |
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0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x60, |
372 |
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373 |
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0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; brl IP */ |
374 |
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0 |
375 |
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}; |
376 |
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uint8_t *gen_code_ptr = *gen_code_pp, *plt_start, *got_start, *vp; |
377 |
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struct ia64_fixup *fixup; |
378 |
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unsigned int offset = 0; |
379 |
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struct fdesc { |
380 |
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long ip; |
381 |
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long gp; |
382 |
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} *fdesc; |
383 |
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int i; |
384 |
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385 |
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if (plt_fixes) { |
386 |
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plt_start = gen_code_ptr; |
387 |
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388 |
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for (i = 0; i < num_plts; ++i) { |
389 |
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if (plt_offset[i]) { |
390 |
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plt_offset[i] = offset; |
391 |
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offset += sizeof(plt_bundle); |
392 |
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393 |
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fdesc = (struct fdesc *) plt_target[i]; |
394 |
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memcpy(gen_code_ptr, plt_bundle, sizeof(plt_bundle)); |
395 |
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ia64_imm64 (gen_code_ptr + 0x02, fdesc->gp); |
396 |
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ia64_imm60b(gen_code_ptr + 0x12, |
397 |
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(fdesc->ip - (long) (gen_code_ptr + 0x10)) >> 4); |
398 |
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gen_code_ptr += sizeof(plt_bundle); |
399 |
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} |
400 |
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} |
401 |
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|
402 |
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for (fixup = plt_fixes; fixup; fixup = fixup->next) |
403 |
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ia64_imm21b(fixup->addr, |
404 |
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((long) plt_start + plt_offset[fixup->value] |
405 |
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- ((long) fixup->addr & ~0xf)) >> 4); |
406 |
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} |
407 |
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408 |
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got_start = gen_code_ptr; |
409 |
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|
410 |
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/* First, create the GOT: */ |
411 |
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for (fixup = ltoff_fixes; fixup; fixup = fixup->next) { |
412 |
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/* first check if we already have this value in the GOT: */ |
413 |
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for (vp = got_start; vp < gen_code_ptr; ++vp) |
414 |
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if (*(uint64_t *) vp == fixup->value) |
415 |
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break; |
416 |
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if (vp == gen_code_ptr) { |
417 |
|
/* Nope, we need to put the value in the GOT: */ |
418 |
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*(uint64_t *) vp = fixup->value; |
419 |
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gen_code_ptr += 8; |
420 |
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} |
421 |
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ia64_imm22(fixup->addr, (long) vp - gp); |
422 |
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} |
423 |
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*gen_code_pp = gen_code_ptr; |
424 |
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} |
425 |
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426 |
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#endif |