/[qemu]/qemu/cpu-i386.h
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Diff of /qemu/cpu-i386.h

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revision 1.39 by bellard, Sun Aug 10 21:47:01 2003 UTC revision 1.40 by bellard, Wed Aug 20 23:02:09 2003 UTC
# Line 73  Line 73 
73  #define CC_S    0x0080  #define CC_S    0x0080
74  #define CC_O    0x0800  #define CC_O    0x0800
75    
76    #define TF_SHIFT   8
77    #define IOPL_SHIFT 12
78    #define VM_SHIFT   17
79    
80  #define TF_MASK                 0x00000100  #define TF_MASK                 0x00000100
81  #define IF_MASK                 0x00000200  #define IF_MASK                 0x00000200
82  #define DF_MASK                 0x00000400  #define DF_MASK                 0x00000400
# Line 85  Line 89 
89  #define VIP_MASK                0x00100000  #define VIP_MASK                0x00100000
90  #define ID_MASK                 0x00200000  #define ID_MASK                 0x00200000
91    
92    /* hidden flags - used internally by qemu to represent additionnal cpu
93       states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
94       using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
95       with eflags. */
96    /* current cpl */
97    #define HF_CPL_SHIFT         0
98    /* true if soft mmu is being used */
99    #define HF_SOFTMMU_SHIFT     2
100    /* true if hardware interrupts must be disabled for next instruction */
101    #define HF_INHIBIT_IRQ_SHIFT 3
102    /* 16 or 32 segments */
103    #define HF_CS32_SHIFT        4
104    #define HF_SS32_SHIFT        5
105    /* zero base for DS, ES and SS */
106    #define HF_ADDSEG_SHIFT      6
107    
108    #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
109    #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
110    #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
111    #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
112    #define HF_SS32_MASK         (1 << HF_CS32_SHIFT)
113    #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
114    
115  #define CR0_PE_MASK  (1 << 0)  #define CR0_PE_MASK  (1 << 0)
116  #define CR0_TS_MASK  (1 << 3)  #define CR0_TS_MASK  (1 << 3)
117  #define CR0_WP_MASK  (1 << 16)  #define CR0_WP_MASK  (1 << 16)
# Line 226  typedef struct CPUX86State { Line 253  typedef struct CPUX86State {
253      uint32_t cc_dst;      uint32_t cc_dst;
254      uint32_t cc_op;      uint32_t cc_op;
255      int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */      int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
256        uint32_t hflags; /* hidden flags, see HF_xxx constants */
257    
258      /* FPU state */      /* FPU state */
259      unsigned int fpstt; /* top of stack index */      unsigned int fpstt; /* top of stack index */
# Line 249  typedef struct CPUX86State { Line 277  typedef struct CPUX86State {
277      SegmentCache tr;      SegmentCache tr;
278      SegmentCache gdt; /* only base and limit are used */      SegmentCache gdt; /* only base and limit are used */
279      SegmentCache idt; /* only base and limit are used */      SegmentCache idt; /* only base and limit are used */
     int cpl;          /* current cpl */  
     int soft_mmu;     /* TRUE if soft mmu is being used */  
280            
281      /* sysenter registers */      /* sysenter registers */
282      uint32_t sysenter_cs;      uint32_t sysenter_cs;
# Line 303  void cpu_x86_load_seg(CPUX86State *s, in Line 329  void cpu_x86_load_seg(CPUX86State *s, in
329  /* wrapper, just in case memory mappings must be changed */  /* wrapper, just in case memory mappings must be changed */
330  static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)  static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
331  {  {
332      s->cpl = cpl;  #if HF_CPL_MASK == 3
333        s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
334    #else
335    #error HF_CPL_MASK is hardcoded
336    #endif
337  }  }
338    
339  /* simulate fsave/frstor */  /* simulate fsave/frstor */

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