/[qemu]/qemu/cpu-i386.h
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revision 1.38 by bellard, Tue Jul 29 20:53:01 2003 UTC revision 1.39 by bellard, Sun Aug 10 21:47:01 2003 UTC
# Line 20  Line 20 
20  #ifndef CPU_I386_H  #ifndef CPU_I386_H
21  #define CPU_I386_H  #define CPU_I386_H
22    
23  #include "config.h"  #include "cpu-defs.h"
 #include <setjmp.h>  
24    
25  #define R_EAX 0  #define R_EAX 0
26  #define R_ECX 1  #define R_ECX 1
# Line 153  Line 152 
152  #define EXCP11_ALGN     17  #define EXCP11_ALGN     17
153  #define EXCP12_MCHK     18  #define EXCP12_MCHK     18
154    
 #define EXCP_INTERRUPT  256 /* async interruption */  
 #define EXCP_HLT        257 /* hlt instruction reached */  
 #define EXCP_DEBUG      258 /* cpu stopped after a breakpoint or singlestep */  
   
 #define MAX_BREAKPOINTS 32  
   
155  enum {  enum {
156      CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */      CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
157      CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */      CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */
# Line 257  typedef struct CPUX86State { Line 250  typedef struct CPUX86State {
250      SegmentCache gdt; /* only base and limit are used */      SegmentCache gdt; /* only base and limit are used */
251      SegmentCache idt; /* only base and limit are used */      SegmentCache idt; /* only base and limit are used */
252      int cpl;          /* current cpl */      int cpl;          /* current cpl */
253        int soft_mmu;     /* TRUE if soft mmu is being used */
254        
255      /* sysenter registers */      /* sysenter registers */
256      uint32_t sysenter_cs;      uint32_t sysenter_cs;
257      uint32_t sysenter_esp;      uint32_t sysenter_esp;
# Line 275  typedef struct CPUX86State { Line 269  typedef struct CPUX86State {
269      int interrupt_request;      int interrupt_request;
270      int user_mode_only; /* user mode only simulation */      int user_mode_only; /* user mode only simulation */
271    
272        /* soft mmu support */
273        /* 0 = kernel, 1 = user */
274        CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
275        CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
276        
277        /* ice debug support */
278      uint32_t breakpoints[MAX_BREAKPOINTS];      uint32_t breakpoints[MAX_BREAKPOINTS];
279      int nb_breakpoints;      int nb_breakpoints;
280      int singlestep_enabled;      int singlestep_enabled;
281        
282      /* user data */      /* user data */
283      void *opaque;      void *opaque;
284  } CPUX86State;  } CPUX86State;

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