125 |
#define PG_ERROR_U_MASK 0x04 |
#define PG_ERROR_U_MASK 0x04 |
126 |
#define PG_ERROR_RSVD_MASK 0x08 |
#define PG_ERROR_RSVD_MASK 0x08 |
127 |
|
|
128 |
|
#define MSR_IA32_APICBASE 0x1b |
129 |
|
#define MSR_IA32_APICBASE_BSP (1<<8) |
130 |
|
#define MSR_IA32_APICBASE_ENABLE (1<<11) |
131 |
|
#define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
132 |
|
|
133 |
|
#define MSR_IA32_SYSENTER_CS 0x174 |
134 |
|
#define MSR_IA32_SYSENTER_ESP 0x175 |
135 |
|
#define MSR_IA32_SYSENTER_EIP 0x176 |
136 |
|
|
137 |
#define EXCP00_DIVZ 0 |
#define EXCP00_DIVZ 0 |
138 |
#define EXCP01_SSTP 1 |
#define EXCP01_SSTP 1 |
139 |
#define EXCP02_NMI 2 |
#define EXCP02_NMI 2 |
253 |
SegmentCache tr; |
SegmentCache tr; |
254 |
SegmentCache gdt; /* only base and limit are used */ |
SegmentCache gdt; /* only base and limit are used */ |
255 |
SegmentCache idt; /* only base and limit are used */ |
SegmentCache idt; /* only base and limit are used */ |
256 |
|
|
257 |
|
/* sysenter registers */ |
258 |
|
uint32_t sysenter_cs; |
259 |
|
uint32_t sysenter_esp; |
260 |
|
uint32_t sysenter_eip; |
261 |
|
|
262 |
/* exception/interrupt handling */ |
/* exception/interrupt handling */ |
263 |
jmp_buf jmp_env; |
jmp_buf jmp_env; |